To maximize the performance of the DACx760 in any application, good layout practices and proper circuit design must be followed. A few recommendations specific to the DACx760 are:

1. As is seen in Figure 9-3, CAP2 is directly connected to the input of the final IOUT amplifier. Any noise or unwanted ac signal routed near the CAP1 and/or CAP2 pins could capacitively couple onto internal nodes and affect IOUT. Therefore, with the QFN package, it is important to avoid routing any digital or HART signal trace over the CAP1 and CAP2 traces.
2. The thermal PAD must be connected to the lowest potential in the system.
3. The +VSENSE connection must be a low-impedance trace connected close to the point of load.
4. AVDD and AVSS must have decoupling capacitors local to the respective pins.
5. The reference capacitor must be placed close to the reference input pin.
6. Avoid routing switching signals near the reference input.
7. For designs that include protection circuits:
   1. Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices.
   2. Use large, wide traces to provide a low-impedance path to divert high-energy transients away from I/O terminals.