8.4.7 Hardware CLR Pin

The CLR pin is an active high input that should be low for normal operation. When this pin is a logic '1', all the outputs are cleared to either zero-scale code or midscale code depending on the status of the CLSLx bit (see reset register). While CLR is high, all LDAC pulses are ignored. When CLR is taken low again, the DAC outputs remain cleared until new data is written to the DAC. The contents of the offset Registers, Gain Registers and DAC input registers are not affected by taking CLR high. Note that the clear action will result in the outputs clearing to the default value instantaneously even if slew rate control is enabled.