SBAS349F August 2005 – June 2016 DAC8812
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | RFBA | I | Establish voltage output for DAC A by connecting to external amplifier output. |
| 2 | VREFA | I | DAC A reference voltage input pin. Establishes DAC A full-scale output voltage. Can be tied to VDD pin. |
| 3 | IOUTA | O | DAC A current output |
| 4 | AGNDA | — | DAC A analog ground |
| 5 | AGNDB | — | DAC B analog ground |
| 6 | IOUTB | O | DAC B current output |
| 7 | VREFB | I | DAC B reference voltage input pin. Establishes DAC B full-scale output voltage. Can be tied to VDD pin. |
| 8 | RFBB | I | Establish voltage output for DAC B by connecting to external amplifier output. |
| 9 | SDI | I | Serial data input; data loads directly into the shift register. |
| 10 | RS | I | Reset pin; active-low input. Input registers and DAC registers are set to all 0s or midscale. Register data = 0x0000 when MSB = 0. Register data = 0x8000 when MSB = 1 for DAC8812. |
| 11 | CS | I | Chip-select; active-low input. Disables shift register loading when high. Transfers serial register data to input register when CS goes high. Does not affect LDAC operation. |
| 12 | DGND | — | Digital ground |
| 13 | VDD | I | Positive power-supply input. Specified range of operation 2.7 V to 5.5 V. |
| 14 | MSB | I | MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can be permanently tied to ground or VDD. |
| 15 | LDAC | I | Load DAC register strobe; level-sensitive active-low. Transfers all input register data to the DAC registers. Asynchronous active-low input. See Table 2 for operation. |
| 16 | CLK | I | Clock input. Positive edge clocks data into shift register. |