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ZHCSHA4B July 2007 – January 2018 DAC8881

PRODUCTION DATA.

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6.7 Timing Characteristics for Figure 2 and Figure 3⁽¹⁾⁽²⁾⁽³⁾

At –40°C to +105°C, unless otherwise noted.

PARAMETER		CONDITIONS	MIN	MAX	UNIT
f_SCLK	Maximum clock frequency	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD		20	MHz
f_SCLK	Maximum clock frequency	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD		25	MHz
t₁	Minumum CS high time	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	50		ns
t₁	Minumum CS high time	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	30		ns
t₂	CS falling edge to SCLK rising edge	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	10		ns
t₂	CS falling edge to SCLK rising edge	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	8		ns
t₃	SCLK falling edge to CS falling edge setup time	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	10		ns
t₃	SCLK falling edge to CS falling edge setup time	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	10		ns
t₄	SCLK low time	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	25		ns
t₄	SCLK low time	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	20		ns
t₅	SCLK high time	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	25		ns
t₅	SCLK high time	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	20		ns
t₆	SCLK cycle time	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	50		ns
t₆	SCLK cycle time	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	40		ns
t₇	SCLK rising edge to CS rising edge	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	10		ns
t₇	SCLK rising edge to CS rising edge	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	10		ns
t₈	Input data setup time	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	5		ns
t₈	Input data setup time	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	5		ns
t₉	Input data hold time	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	5		ns
t₉	Input data hold time	3.6 ≤ DV_DD ≤ 5.5 , 2.7 ≤ IOV_DD ≤ DV_DD	5		ns
t₁₀	SDO active from CS falling edge	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD		15	ns
t₁₀	SDO active from CS falling edge	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD		10	ns
t₁₁	SDO data valid from SCLK falling edge	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD		20	ns
t₁₁	SDO data valid from SCLK falling edge	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD		15	ns
t₁₂	SDO data hold from SCLK rising edge	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	25		ns
t₁₂	SDO data hold from SCLK rising edge	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	20		ns
t₁₃	SDO High-Z from CS rising edge	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD		8	ns
t₁₃	SDO High-Z from CS rising edge	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD		5	ns
t₁₄	CS rising edge to LDAC falling edge	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	10		ns
t₁₄	CS rising edge to LDAC falling edge	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	5		ns
t₁₅	LDAC pulse width	2.7 ≤ DV_DD< 3.6 V, 2.7 ≤ IOV_DD ≤ DV_DD	15		ns
t₁₅	LDAC pulse width	3.6 ≤ DV_DD ≤ 5.5 V, 2.7 ≤ IOV_DD ≤ DV_DD	10		ns

(1) All input signals are specified with t_R = t_F = 2ns (10% to 90% of IOV_DD) and timed from a voltage level of IOV_DD/2.

(2) Specified by design. Not production tested.

(3) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.

Figure 1. Timing Diagram of Standalone Operation Without SDO

Figure 2. Timing Diagram of Standalone Operation With SDO

Figure 3. Timing Diagram of Daisy Chain Mode, Two Cascaded Devices

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6.7 Timing Characteristics for Figure 2 and Figure 3(1)(2)(3)

6.7 Timing Characteristics for Figure 2 and Figure 3⁽¹⁾⁽²⁾⁽³⁾