ZHCSHA4B July   2007  – January 2018 DAC8881

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics for
    7. 6.7 Timing Characteristics for and
    8. 6.8 Typical Characteristics: VDD = +5 V
    9. 6.9 TYpical Characteristics: VDD = +2.7 V
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Output
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Output Range
      4. 7.3.4  Input Data Format
      5. 7.3.5  Hardware Reset
      6. 7.3.6  Power-On Reset
      7. 7.3.7  Program Reset Value
      8. 7.3.8  Power Down
      9. 7.3.9  Double-Buffered Interface
      10. 7.3.10 Load DAC Pin (LDAC)
        1. 7.3.10.1 Synchronous Mode
        2. 7.3.10.2 Asynchronous Mode
      11. 7.3.11 1.8 V to 5.5 V Logic Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
        1. 7.4.1.1 Input Shift Register
          1. 7.4.1.1.1 Stand-Alone Mode
          2. 7.4.1.1.2 Daisy-Chain Mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using The DAC8881
    2. 8.2 Typical Application
      1. 8.2.1 DAC8881 Sample Hold Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 System Example
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Reference Inputs

The reference high input, VREFH, can be set to any voltage in the range of 1.25 V to AVDD. The reference low input, VREFL, can be set to any voltage in the range of –0.2 V to +0.2 V (to provide a small offset to the output of the DAC8881, if desired). The current into VREFH and out of VREFL depends on the DAC code, and can vary from approximately 0.5mA to 1mA in the gain = 1X mode of operation. The reference high and low inputs appear as varying loads to the external reference circuit. If the external references can source or sink the required current, and if low impedance connections are made to the VREFH and VREFL pins, external reference buffers are not required. Figure 67 shows a simple configuration of the DAC8881 using external references without force/sense reference buffers.

Kelvin sense connections for the reference high and low are included on the DAC8881. When properly used with external reference buffer op amps, these reference Kelvin sense pins ensure that the driven reference high and low voltages remain stable versus varying reference load currents. Figure 69 shows an example of a reference force/sense configuration of the DAC8881 operating from a single analog supply voltage. Both the VREFL and VREFH reference voltages are set to levels of 100 mV from the DAC8881 supply rails, and are derived from a 5-V external reference. Figure 71 and Figure 70 illustrate the effect of not using the reference force/sense buffers to drive the DAC8881 VREFL and VREFH pins. A slight degradation in INL and DNL performance of approximately 0.1 LSB may be seen without the use of the force/sense buffer configuration.

DAC8881 ai_buf_ref_bas422.gifFigure 69. Buffered References (VREFH = +4.900 V and VREFL = 100 mV)
DAC8881 ai_inl_dnl_2_bas422.gifFigure 70. Linearity and Differential Linearity Error
for Figure 67 without Reference Buffers
DAC8881 ai_inl_dnl_1_bas422.gifFigure 71. Linearity and Differential Linearity Error
for Figure 69 with Reference Buffers