Table 2. Timing Requirements for Integration Sequence Timing

8.3.1 Dual Switched Integrator: Basic Integration Cycle

The topology of the front end of the DDC264 is an analog integrator as shown in Figure 20. In this diagram, only input IN1 is shown. The input stage consists of an operational amplifier, a selectable feedback capacitor network (C_F), and several switches that implement the integration cycle. The timing relationships of all of the switches shown in Figure 20 are illustrated in Figure 21. Figure 21 conceptualizes the operation of the integrator input stage of the DDC264 and must not be used as an exact timing tool for design.

See Figure 22 for the block diagrams of the reset, integrate, wait, and convert states of the integrator section of the DDC264. This internal switching network is controlled externally with the convert pin (CONV) and the system clock (CLK). For the best noise performance, CONV must be synchronized with the falling edge of CLK. TI recommends toggling CONV within ±10 ns of the falling edge of CLK.

The noninverting inputs of the integrators are connected to the QGND pin. Consequently, the DDC264 analog ground, QGND, must be as clean as possible. In Figure 20, the feedback capacitors (C_F) are shown in parallel between the inverting input and output of the operational amplifier. At the beginning of a conversion, the switches S_A/D, S_INTA, S_INTB, S_REF1, S_REF2, and S_RESET are set (see Figure 21).

At the completion of an A/D conversion, the charge on the integration capacitor (C_F) is reset with S_REF1 and S_RESET (see Figure 21 and Figure 22a). This process is done during reset. In this manner, the selected capacitor is charged to the reference voltage, VREF. Once the integration capacitor is charged, S_REF1 and S_RESET are switched so that VREF is no longer connected to the amplifier circuit while it waits to begin integrating (see Figure 22b). With the rising edge of CONV, S_INTA closes, which begins the integration of side A. This process puts the integrator stage into its integrate mode (see Figure 22c).

Charge from the input signal is collected on the integration capacitor, causing the voltage output of the amplifier to decrease. The falling edge of CONV stops the integration by switching the input signal from side A to side B (S_INTA and S_INTB). Prior to the falling edge of CONV, the signal on side B was converted by the A/D converter and reset during the time that side A was integrating. With the falling edge of CONV, side B starts integrating the input signal. At this point, the output voltage of the side A operational amplifier is presented to the input of the A/D converter (see Figure 22d).

A special elecrostatic discharge (ESD) structure protects the inputs but does not increase current leakage on the input pins.

Figure 20. Basic Integration Configuration

Figure 21. Integration Timing (see Figure 20)

Figure 22. Four Configurations of the Front-End Integrators

8.3.2 Integration Capacitors

There are four different capacitor configurations available on-chip for both sides of every channel in the DDC264. These internal capacitors are trimmed in production to achieve the specified performance for range error of the DDC264. The range control bits (Range[1:0]) set the capacitor value for all integrators. Consequently, all inputs and both sides of each input always have the same full-scale range. Table 3 shows the capacitor value selected for each range selection.

8.3.3 Voltage Reference

The external voltage reference is used to reset the integration capacitors before an integration cycle begins. It is also used by the A/D converter while the converter is measuring the voltage stored on the integrators after an integration cycle ends. During this sampling, the external reference must supply the charge required by the A/D converter. For an integration time of 333 µs, this charge translates to an average V_REF current of approximately 825 µA. The amount of charge required by the A/D converter is independent of the integration time; therefore, increasing the integration time lowers the average current. For example, an integration time of 800 µs lowers the average V_REF current to 340 µA.

8.3.4 Serial Data Output and Control Interface

8.3.4.5 Data Retrieval

The data from the last conversion are available for retrieval on the falling edge of DVALID (see Figure 23 and Table 5). Data are shifted out on the falling edge of the data clock, DCLK.

Make sure not to retrieve data around changes in CONV because this change can introduce noise. Stop activity on DCLK at least 2 µs before or after a CONV transition.

Setting the format bit = 0 (16-bit output word) reduces the time required to retrieve data by 20% because there are fewer bits to shift out. This technique can be useful in multichannel systems requiring only 16 bits of resolution.

Figure 23. Digital Interface Timing Diagram for Data Retrieval From a Single DDC264

Table 5. Timing for DDC264 Data Retrieval

		MIN	TYP	MAX	UNIT
tPDCDV	Propagation delay from falling edge of CLK to DVALID Low	10			ns
tPDDCDV	Propagation delay from falling edge of DCLK to DVALID High	5			ns
tHDDODV	Hold time that DOUT is valid before the falling edge of DVALID		400		ns
tHDDODC	Hold time that DOUT is valid after falling edge of DCLK	4			ns
tPDDCDO	Propagation delay from falling edge of DCLK to valid DOUT			25	ns

8.3.4.5.1 Cascading Multiple Converters

Multiple DDC264 devices can be connected in a serial configuration; see Figure 24.

DOUT can be used with DIN to daisy-chain multiple DDC264 devices together to minimize wiring. In this mode of operation, the serial data output is shifted through multiple DDC264s; see Figure 24.

Figure 25 shows the timing diagram when the DIN input is used to daisy-chain several devices. Table 6 gives the timing specification for data retrieval using DIN.

Figure 24. Daisy-Chained DDC264s

1. See Cascading Multiple Converters.

Figure 25. Timing Diagram When Using DDC264 DIN Function

Table 6. Timing for DDC264 Data Retrieval Using DIN

		MIN	TYP	MAX	UNIT
tSTDIDC	Setup time from DIN to falling edge of DCLK	10			ns
tHDDIDC	Hold time for DIN after falling edge of DCLK	10			ns

8.3.4.5.2 Retrieval Before CONV Toggles

In this method, data retrieval begins soon after DVALID goes low and finishes before CONV toggles, as shown in Figure 26. For best performance, data retrieval must stop t_SDCV before CONV toggles. This method is most appropriate for longer integration times and yields the best performance results as the output interface toggling noise does not interfere with the ADC conversion operation. The maximum time available for readback is
t_INT – t_CMDR – t_SDCV. The maximum number of DDC264s that can be daisy-chained together (format = 1) is calculated by Equation 1.

Equation 1.

Note: (16 × 64)τ_DCLK is used for format = 0, where τ_DCLK is the period of the data clock

For example, if t_INT = 1000 µs and DCLK = 20 MHz, the maximum number of DDC264s with format = 1 is shown in Equation 2.

Equation 2.

or 14 DDC264s for format = 0

Figure 26. Readback Before CONV Toggles

Table 7. Timing for Readback

		MIN	TYP	MAX	UNIT
tSDCV	Data retrieval shutdown before or after edge of CONV	2			µs

8.3.4.5.3 Retrieval After CONV Toggles

For shorter integration times, more time is available if data retrieval begins after CONV toggles and ends before the new data are ready. Data retrieval must wait t_SDCV after CONV toggles before beginning. See Figure 27 for an example of this timing sequence. The maximum time available for retrieval is t_DR – (t_SDCV + t_HDDODV), regardless of t_INT. The maximum number of DDC264s that can be daisy-chained together with format = 1 is calculated by Equation 3.

Equation 3.

Note: (16 × 64)τ_DCLK is for format = 0

For DCLK = 20 MHz, the maximum number of DDC264s is four (or five for format = 0).

Figure 27. Readback After CONV Toggles

8.3.4.5.4 Retrieval Before and After CONV Toggles

For the absolute maximum time for data retrieval, data can be retrieved before and after CONV toggles. Nearly all of t_INT is available for data retrieval. Figure 28 illustrates how this process is done by combining the two previous methods. Pause the retrieval during CONV toggling to prevent digital noise, as discussed previously, and finish before the next data are ready. The maximum number of DDC264s that can be daisy-chained together with format = 1 is calculated by Equation 4.

Equation 4.

Note: (16 × 64)τ_DCLK is used for format = 0

For t_INT = 400 µs and DCLK = 20 MHz, the maximum number of DDC264s is six (or seven for format = 0).

Figure 28. Readback Before and After CONV Toggles

8.5.1 Reset (RESET)

The DDC264 is reset asynchronously by taking the RESET input low, as shown in Figure 29. Make sure the release pulse is a minimum of t_RST wide. It is very important that RESET is glitch-free to avoid unintentional resets. The Configuration Register must be programmed immediately afterwards. After programming the DDC264, wait at least four conversions before using the data.

Figure 29. Reset Timing

8.5.2 Configuration Register — Read and Write Operations

The Configuration Register must be programmed after power-up or a device reset. The DIN_CFG, CLK_CFG, and RESET pins are used to write to this register. When beginning a write operation, hold CONV low and strobe RESET; see Figure 30. Then begin shifting in the configuration data on DIN_CFG. Data are written to the Configuration Register most significant bit first. The data are internally latched on the falling edge of CLK_CFG. Partial writes to the Configuration Register are not allowed, that is, make sure to send all 16 bits when updating the register.

Optional readback of the Configuration Register is available immediately after the write sequence. During readback, 320 '0's, then the 16-bit configuration data followed by a 4-bit revision ID and the check pattern are shifted out on the DOUT pin on the rising edge of DCLK. The check pattern can be used to check or verify the DOUT functionality.

Table 1. Configuration Register Bit Assignments

Table 10. Clkdiv Operation