ZHCSFA7A July 2016 – April 2017 DIX4192-Q1
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 说明 （续）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 RESET Operation
- 9.3.2 Master and Reference Clocks
- 9.3.3 Audio Serial Port Operation
- 9.3.4 Overview of the AES3 Digital Audio Interface Protocol
- 9.3.5 Digital Interface Transmitter (DIT) Operation
- 9.3.6 Digital Interface Receiver (DIR) Operation
- 9.3.7 General-Purpose Digital Outputs
- 9.3.8 Interrupt Output
- 9.4 Device Functional Modes
- 9.5 Register Maps
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文档支持
- 14机械、封装和可订购信息
12 Layout
12.1 Layout Guidelines
TI recommends to use one ground plane for the DIX4192-Q1. While using one ground plane, it is best to ensure that analog and digital circuitry be sufficiently partitioned on the PCB so that analog and digital return currents do not cross.
- Decoupling capacitors must be placed as close to power pins as possible (VCC, VDD33, VDD18, VIO).
- Further guidelines can be found in Layout Example.
12.2 Layout Example
Figure 85. DIX4192-Q1 Board Layout