ZHCSP43C november   2021  – july 2023 DLP160AP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

Figure 5-1 FQT Package 35-Pin
GUID-20210722-CA0I-CVKQ-HLHM-2TMHXPFRVDD1-low.gif
Table 5-1 Connector Pins
PIN(1) PACKAGE NET LENGTH (mm)(2)
NAME NO. TYPE SIGNAL DATA RATE DESCRIPTION
DATA INPUTS
D_N(0) A2 I SubLVDS Double Data, negative 1.91
D_N(1) A4 I SubLVDS Double Data, negative 3.6
D_N(2) D4 I SubLVDS Double Data, negative 3.28
D_N(3) E2 I SubLVDS Double Data, negative 1.67
D_P(0) A3 I SubLVDS Double Data, positive 2.03
D_P(1) B4 I SubLVDS Double Data, positive 3.7
D_P(2) E4 I SubLVDS Double Data, positive 3.39
D_P(3) E3 I SubLVDS Double Data, positive 1.77
DCLK_N C3 I SubLVDS Double Clock, negative 2.29
DCLK_P C4 I SubLVDS Double Clock, positive 2.4
CONTROL INPUTS
LS_WDATA C12 I LPSDR Single Write data for low-speed interface 1.55
LS_CLK C13 I LPSDR Single Clock for low-speed interface 1.65
DMD_DEN_ARSTZ D12 I LPSDR Single Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 1.57
LS_RDATA D13 O LPSDR Single 1.43
POWER
VBIAS(3) A13 Power Supply voltage for positive bias level at micromirrors
VOFFSET(3) E13 Power Supply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes. Supply voltage for offset level at micromirrors.
VRESET(3) A14 Power Supply voltage for negative reset level at micromirrors.
VDD B12 Power Supply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs. Supply voltage for normal high level at micromirror address electrodes.
VDD B14 Power
VDD C1 Power
VDD C14 Power
VDD C2 Power
VDD E14 Power
VDDI B1 Power Supply voltage for SubLVDS receivers.
VDDI D1 Power
VSS A1 Ground Common return. Ground for all power.
VSS A12 Ground
VSS B13 Ground
VSS B2 Ground
VSS B3 Ground
VSS D14 Ground
VSS D2 Ground
VSS D3 Ground
VSS E1 Ground
VSS E12 Ground
(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR). See JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQP ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 in/ns.
Propagation delay = 0.265 ns/inch = 265 ps/in = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.
Table 5-2 Test Pads
NUMBER SYSTEM BOARD
A5 Do not connect
A6 Do not connect
A7 Do not connect
A8 Do not connect
A9 Do not connect
A10 Do not connect
A11 Do not connect
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