ZHCSP44D October   2021  – October 2024 DLP160CP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
    8. 5.8  Switching Characteristics
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application—nHD Mode
      2. 7.2.2 Typical Application—HD Mode
      3. 7.2.3 Design Requirements
      4. 7.2.4 Detailed Design Procedure
      5. 7.2.5 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply Power-Up Procedure
    2. 8.2 Power Supply Power-Down Procedure
    3. 8.3 Power Supply Sequencing Requirements
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 10.1.2 Device Nomenclature
      3. 10.1.3 Device Markings
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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8 Power Supply Recommendations

The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required. DMD power-up and power-down sequencing is strictly controlled by the DLPA200x/DLPA3000 devices.

CAUTION:

For reliable operation of the DMD, the following power supply sequencing requirements must be followed. Failure to adhere to the prescribed power-up and power-down procedures may affect device reliability.

VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and power-down operations. Failure to meet any of the below requirements results in a significant reduction in the reliability and lifetime of the DMD. Refer to the Power-Up Sequence Delay Requirement. VSS must also be connected.
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