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ZHCSP44D October 2021 – October 2024 DLP160CP

PRODUCTION DATA

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机械数据 (封装 | 引脚)

FQT|42
- MCLG043

散热焊盘机械数据 (封装 | 引脚)

订购信息

zhcsp44d_oa

8.3 Power Supply Sequencing Requirements

DLP160CP Power Supply Sequencing Requirements (Power Up and Power Down)

A. Refer to the Power-Up Sequence Delay Requirement for critical power-up sequence delay requirements.

B. To prevent excess current, the supply voltage delta |V_BIAS – V_OFFSET| must be less than specified in Section 5.4. OEMs may find that the most reliable way to ensure this is to power V_OFFSET prior to V_BIAS during power-up and to remove V_BIAS prior to V_OFFSET during power-down. Refer to Power-Up Sequence Delay Requirement for power-up delay requirements.

C. To prevent excess current, the supply voltage delta |V_BIAS – V_RESET| must be less than the specified limit shown in Section 5.4.

D. When system power is interrupted, the DLPA200x/DLPA3000 initiates hardware power-down that disables V_BIAS, V_RESET, and V_OFFSET after the micromirror park sequence.

E. The drawing is not to scale and details are omitted for clarity.

Figure 8-1 Power Supply Sequencing Requirements (Power Up and Power Down)

Table 8-1 Power-Up Sequence Delay Requirement

PARAMETER		MIN	MAX	UNIT
t_DELAY	Delay requirement from V_OFFSET power up to V_BIAS power up	2		ms
V_OFFSET	The supply voltage level at the beginning of power-up sequence delay		6	V
V_BIAS	The supply voltage level at end of power-up sequence delay		6	V

DLP160CP Power-Up Sequence Delay Requirement

This requirement applies only to the DLPA200x.

Refer to Power-Up Sequence Delay Requirement for V_OFFSET and V_BIAS supply voltage levels during power-up sequence delay.

Figure 8-2 Power-Up Sequence Delay Requirement