米6体育平台手机版

ZHCSJE6C february 2019 – july 2023 DLP2010

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机械数据 (封装 | 引脚)

FQJ|40
- MCLG028B

散热焊盘机械数据 (封装 | 引脚)

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zhcsje6c_oa

9.3 Power Supply Sequencing Requirements

DLP controller and PMIC controls start of DMD operation

Mirror park sequence starts

Mirror park sequence ends. DLP controller and PMIC disables VBIAS, VOFFSET, and VRESET.

Power off.

Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements.

When system power is interrupted, the ASIC driver initiates hardware the power-down sequence, that disables VBIAS, VRESET and VOFFSET after the micromirror park sequence is complete. Software the power-down sequence, disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through software control.

To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Section 6.4.

Drawing is not to scale and details are omitted for clarity.

Figure 9-1 Power Supply Sequencing Requirements

Table 9-1 Power-Up Sequence Delay Requirement

PARAMETER		MIN	MAX	UNIT
t_DELAY	Delay requirement from VOFFSET power up to VBIAS power up	2		ms
VOFFSET	Supply voltage level during power–up sequence delay (see Figure 9-2)		6	V
VBIAS	Supply voltage level during power–up sequence delay (see Figure 9-2)		6	V

Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.

Figure 9-2 Power-Up Sequence Delay Requirement