米6体育平台手机版

DLPS119B December 2018 – May 2022 DLP2010NIR

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

FQJ|40

散热焊盘机械数据 (封装 | 引脚)

订购信息

9.3 Power Supply Sequencing Requirements

A. Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements.

B. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down. Refer to Table 9-1 and Figure 9-2 for power-up delay requirements.

C. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Recommended Operating Conditions.

D. When system power is interrupted, the ASIC driver initiates hardware power-down that disables VBIAS, VRESET and VOFFSET after the Micromirror Park Sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the Micromirror Park Sequence through software control.

E. Drawing is not to scale and details are omitted for clarity.

Figure 9-1 Power Supply Sequencing Requirements (Power Up and Power Down)

Table 9-1 Power-Up Sequence Delay Requirement

PARAMETER		MIN	MAX	UNIT
t_DELAY	Delay requirement from VOFFSET power up to VBIAS power up	2		ms
V_OFFSET	Supply voltage level during power–up sequence delay (see Figure 9-2)		6	V
V_BIAS	Supply voltage level during power–up sequence delay (see Figure 9-2)		6	V

Note: Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.

Figure 9-2 Power-Up Sequence Delay Requirement