The power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
During power-down, it is not mandatory to stop
driving VBIAS prior to VOFFSET, but it is a strict
requirement that the delta between VBIAS and VOFFSET must
be within the specified limit shown in Section 6.4 (Refer to
Note 2 for Figure 9-1).
During power-down, the DMD’s LPSDR input pins
must be less than VDDI, the specified limit shown in Section 6.4.
During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed previously and in Figure 9-1.