米6体育平台手机版

ZHCSOH3B July 2021 – May 2022 DLP300S

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机械数据 (封装 | 引脚)

FQK|57
- MCLG029B

散热焊盘机械数据 (封装 | 引脚)

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zhcsoh3b_oa

9.3 Power Supply Sequencing Requirements

A. Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements.

B. To prevent excess current, the supply voltage delta |V_BIAS – V_OFFSET| must be less than specified in Section 6.4. OEMs may find that the most reliable way to ensure this is to power V_OFFSET prior to V_BIAS during power-up and to remove V_BIAS prior to V_OFFSET during power-down. Refer to Table 9-1 and Figure 9-2 for power-up delay requirements.

C. To prevent excess current, the supply voltage delta |V_BIAS – V_RESET| must be less than specified limit shown in Section 6.4.

D. When system power is interrupted, the ASIC driver initiates hardware power-down that disables V_BIAS, V_RESET and V_OFFSET after the Micromirror Park Sequence. Software power-down disables V_BIAS, V_RESET, and V_OFFSET after the Micromirror Park Sequence through software control.

E. Drawing is not to scale and details are omitted for clarity.

Figure 9-1 Power Supply Sequencing Requirements (Power Up and Power Down)

Table 9-1 Power-Up Sequence Delay Requirement

PARAMETER		MIN	MAX	UNIT
t_DELAY	Delay requirement from V_OFFSET power up to V_BIAS power up	2		ms
V_OFFSET	Supply voltage level during power–up sequence delay (see Figure 9-2)		6	V
V_BIAS	Supply voltage level during power–up sequence delay (see Figure 9-2)		6	V

A. Refer to Table 9-1 for V_OFFSET and V_BIAS supply voltage levels during power-up sequence delay.

Figure 9-2 Power-Up Sequence Delay Requirement