米6体育平台手机版

ZHCSL02C March 2020 – March 2023 DLP3021-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

FQR|54
- MCCC009

散热焊盘机械数据 (封装 | 引脚)

订购信息

zhcsl02c_oa

6.7 Timing Requirements

Over Section 6.4 unless otherwise noted.

		MIN	MAX	UNIT
DMD MIRROR AND SRAM CONTROL LOGIC SIGNALS
t_SU	Setup time SAC_BUS low before SAC_CLK↑	1.0		ns
t_H	Hold time SAC_BUS low after SAC_CLK↑	1.0		ns
t_SU	Setup time DAD_BUS high before SAC_CLK↑	1.0		ns
t_H	Hold time DAD_BUS after SAC_CLK↑	1.0		ns
t_C	Cycle time SAC_CLK	12.5	16.67	ns
t_W	Pulse width 50% to 50% reference points: SAC_CLK high or low	5.0		ns
t_R	Rise time 20% to 80% reference points: SAC_CLK		2.5	ns
t_F	Fall time 80% to 20% reference points: SAC_CLK		2.5	ns
DMD DATA PATH AND LOGIC CONTROL SIGNALS
t_SU	Setup time DATA(14:0) before DCLK↑ or DCLK↓	1.0		ns
t_H	Hold time DATA(14:0) after DCLK↑ or DCLK↓	1.0		ns
t_SU	Setup time SCTRL before DCLK↑ or DCLK↓	1.0		ns
t_H	Hold time SCTRL after DCLK↑ or DCLK↓	1.0		ns
t_SU	Setup time TRC before DCLK↑ or DCLK↓	1.0		ns
t_H	Hold time TRC after DCLK↑ or DCLK↓	1.0		ns
t_SU	Setup time LOADB low before DCLK↑	1.0		ns
t_H	Hold time LOADB low after DCLK↓	1.0		ns
t_SU	Setup time RESET_STROBE high before DCLK↑	1.0		ns
t_H	Hold time RESET_STROBE after DCLK↑	3.5		ns
t_C	Cycle time DCLK	12.5	16.67	ns
t_W	Pulse width 50% to 50% reference points: DCLK high or low	5.0		ns
t_W(L)	Pulse width 50% to 50% reference points: LOADB low	7.0		ns
t_W(H)	Pulse width 50% to 50% reference points: RESET_STROBE high	7.0		ns
t_R	Rise time 20% to 80% reference points: DCLK, DATA, SCTRL, TRC, LOADB		2.5	ns
t_F	Fall time 80% to 20% reference points: DCLK, DATA, SCTRL, TRC, LOADB		2.5	ns
JTAG BOUNDARY SCAN CONTROL LOGIC SIGNALS
f_TCK	Clock frequency TCK		10	MHz
t_C	Cycle time TCK	100		ns
t_W	Pulse width 50% to 50% reference points: TCK high or low	10		ns
t_SU	Setup time TDI valid before TCK↑	5		ns
t_H	Hold time TDI valid after TCK↑	25		ns
t_SU	Setup time TMS valid before TCK↑	5		ns
t_H	Hold time TMS valid after TCK↑	25		ns
t_R	Rise time 20% to 80% reference points: TCK, TDI, TMS		2.5	ns
t_R	Fall time 80% to 20% reference points: TCK, TDI, TMS		2.5	ns

Figure 6-2 DMD Mirror and SRAM Control Logic Timing Requirements

Figure 6-3 DMD Data Path and Control Logic Timing Requirements

Figure 6-4 JTAG Boundary Scan Control Logic Timing Requirements