The DMD uses 4 standard JTAG signals for sending and receiving boundary scan test data. TCK is the test clock used to drive an IEEE 1149.1 TAP state machine and logic. TMS directs the next state of the TAP state machine. TDI is the scan data input and TDO is the scan data output.

The DMD does not support IEEE 1149.1 signals TRST (Test Logic Reset) and RTCK (Returned Test Clock). Boundary scan cells on the DMD are Observe-Only. To initiate the JTAG boundary scan operation on the DMD, a minimum of 6 TCK clock cycles are required after TMS is set to logic high.

Refer to Figure 7-4 for a JTAG system board routing example.

Figure 7-4 System Interface Connection to DLP Products Controller

The DMD Device ID can be read via the JTAG interface. The ID and 32-bit shift order is shown in Figure 7-5.

Figure 7-5 DMD Device ID and 32-bit Shift Order

Refer to Figure 7-6 for a JTAG boundary scan block diagram for the DMD. These show the pins and the scan order that are observed during the JTAG boundary scan.

Figure 7-6 JTAG Boundary Scan Path

Refer to Figure 7-7 for a functional block diagram of the JTAG control logic.

Figure 7-7 JTAG Functional Block Diagram