米6体育平台手机版

ZHCSJL8A April 2019 – September 2019 DLP3034-Q1

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

FYJ|149
- MCPS004A

散热焊盘机械数据 (封装 | 引脚)

订购信息

zhcsjl8a_oa

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽³⁾

PARAMETER		TEST CONDITIONS⁽²⁾	MIN	TYP	MAX	UNIT
V_OH	High level output voltage	VCC = 2.25 V	1.7			V
V_OH	High level output voltage	I_OH = –8 mA	1.7			V
V_OH2	High level output voltage⁽⁷⁾	VREF = 1.8 V	1.44			V
V_OH2	High level output voltage⁽⁷⁾	I_OH = –2 mA	1.44			V
V_OL	Low level output voltage	VCC = 2.75 V			0.4	V
V_OL	Low level output voltage	I_OL = 8 mA			0.4	V
V_OL2	Low level output voltage⁽⁷⁾	VREF = 1.8 V			0.36	V
V_OL2	Low level output voltage⁽⁷⁾	I_OL = 2 mA			0.36	V
I_OZ	Output high impedance current	VREF = 1.95 V	–10			µA
		V_OL = 0 V	–10
		VREF = 1.95 V			10
		V_OH = VREF			10
I_IL	Low level input current⁽⁴⁾	VREF = 1.95 V	–5			µA
I_IL	Low level input current⁽⁴⁾	V_I = 0 V	–5			µA
I_IH	High level input current⁽⁴⁾	VREF = 1.95 V			6	µA
I_IH	High level input current⁽⁴⁾	V_I = VREF			6	µA
I_IL2	Low level input current⁽⁵⁾	VREF = 1.95 V	–785			µA
I_IL2	Low level input current⁽⁵⁾	V_I = 0 V	–785			µA
I_IH2	High level input current⁽⁵⁾	VREF = 1.95 V			6	µA
I_IH2	High level input current⁽⁵⁾	V_I = VREF			6	µA
I_IL3	Low level input current⁽⁶⁾	VREF = 1.95 V	–5			µA
I_IL3	Low level input current⁽⁶⁾	V_I = 0 V	–5			µA
I_IH3	High level input current⁽⁶⁾	VREF = 1.95 V			785	µA
I_IH3	High level input current⁽⁶⁾	V_I = VREF			785	µA
CURRENT
I_REF	Current at V_REF = 1.95 V	f_DCLK = 80 MHz			2.80	mA
I_cc	Current at V_CC = 2.75 V	f_DCLK = 80 MHz			59.90	mA
I_OFFSET	Current at V_OFFSET = 8.75 V				2.93	mA
I_BIAS	Current at V_BIAS = 16.5 V				2.30	mA
I_RESET	Current at V_RESET = –10.5 V				–2.00	mA
POWER⁽¹⁾
P_REF	Power at V_REF = 1.95 V	f_DCLK = 80 MHz			5.46	mW
P_CC	Power at V_CC = 2.75 V	f_DCLK = 80 MHz			164.73	mW
P_OFFSET	Power at V_OFFSET = 8.75 V				25.64	mW
P_BIAS	Power at V_BIAS = 16.5 V				37.95	mW
P_RESET	Power at V_RESET = –10.5 V				21.00	mW
P_TOTAL	Total power at nominal conditions	f_DCLK = 80 MHz		105	254.77	mW
CAPACITANCE
C_IN	Input pin capacitance	ƒ = 1 MHz			20	pF
C_A	Analog pin capacitance (TEMP_PLUS and TEMP_MINUS pins)	ƒ = 1 MHz			65	pF
C_o	Output pin capacitance	ƒ = 1 MHz			20	pF

(1) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, V_RESET. All V_SS connections are also required.

(2) All voltage values are with respect to the ground pins (V_SS).

(3) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

(4) Specification is for LVCMOS input pins, which do not have pull up or pull down resistors. See Pin Configuration and Functions section.

(5) Specification is for LVCMOS input pins which do have pull up resistors (JTAG: TDI, TMS). See Pin Configuration and Functions section.

(6) Specification is for LVCMOS input pins which do have pull down resistors. See Pin Configuration and Functions section.

(7) Specification is for LVCMOS JTAG output pin TDO.