7.3.7 DMD JTAG Interface

The DMD uses 4 standard JTAG signals for sending and receiving boundary scan test data. TCK is the test clock used to drive an IEEE 1149.1 TAP state machine and logic. TMS directs the next state of the TAP state machine. TDI is the scan data input and TDO is the scan data output.

The DMD does not support IEEE 1149.1 signals TRST (Test Logic Reset) and RTCK (Returned Test Clock). Boundary scan cells on the DMD are Observe-Only. To initiate the JTAG boundary scan operation on the DMD, a minimum of 6 TCK clock cycles are required after TMS is set to logic high.

Refer to Figure 13 for a JTAG system board routing example. The DLPC120-Q1 can be enabled to perform an in system boundary scan test. See DLPC120-Q1 Programmer's Guide for information about this test.

Figure 13. System Interface Connection to DLPC120-Q1

The DMD Device ID can be read via the JTAG interface. The ID and 32-bit shift order is shown in Figure 14.

Figure 14. DMD Device ID and 32-bit Shift Order

Refer to Figure 15 for a JTAG boundary scan block diagram for the DMD. These show the pins and the scan order that are observed during the JTAG boundary scan.

Figure 15. JTAG Boundary Scan Path

Refer to Figure 16 for a functional block diagram of the JTAG control logic.

Figure 16. JTAG Functional Block Diagram