6.1 Absolute Maximum Ratings
See (1)
| |
MIN |
MAX |
UNIT |
| SUPPLY VOLTAGE |
| VREF |
LVCMOS logic supply voltage(2) |
–0.5 |
4 |
V |
| VCC |
LVCMOS logic supply voltage(2) |
–0.5 |
4 |
V |
| VOFFSET |
Mirror electrode and HVCMOS voltage(2) |
–0.5 |
8.75 |
V |
| VBIAS |
Mirror electrode voltage |
–0.5 |
17 |
V |
| |VBIAS – VOFFSET| |
Supply voltage delta(3) |
|
8.75 |
V |
| VRESET |
Mirror electrode voltage |
–11 |
0.5 |
V |
| Input voltage: other Inputs |
See (2) |
–0.5 |
VREF + 0.3 |
V |
| fDCLK |
Clock frequency |
60 |
80 |
MHz |
| ITEMP_DIODE |
Temperature diode current |
|
500 |
µA |
| ENVIRONMENTAL |
| TARRAY |
Operating DMD array temperature(4) |
–40 |
105 |
°C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Unless otherwise indicated, these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND (VSS). VBIAS, VCC, VOFFSET, VREF, VRESET, and VSS are required to operate the DMD.
(3) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than or equal to 8.75 V.