The DLP3310 DMD is connected to a PCB or a Flex circuit using an interposer. For additional layout guidelines regarding length matching, impedance, etc. see the DLPC3437 controller datasheet. For a detailed layout example refer to the layout design files. Some layout guidelines for routing to the DLP3310 DMD are:

• Match lengths for the LS_WDATA and LS_CLK signals.
• Minimize vias, layer changes, and turns for the HS bus signals. Refer to Figure 10-1.
• Minimum of two 220-nF (35 V) capacitors - one close to V_BIAS pin. Capacitors C10 and C14 in Figure 10-1.
• Minimum of two 220-nF (35 V) capacitors - one close to each V_RST pin. Capacitors C11 and C13 in Figure 10-1.
• Minimum of two 220-nF (35 V) capacitors - one close to each V_OFS pin. Capacitors C4 and C12 in Figure 10-1.
• Minimum of four 220-nF (10 V) capacitors - two close to each side of the DMD. Capacitors C1, C3, C2, and C5 in Figure 10-1.