ZHCSJA4B January   2019  – May 2022 DLP4500

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Chipset Component Usage Specification
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
    5. 8.5 Micromirror Array Temperature Calculation
      1. 8.5.1 Package Thermal Resistance
      2. 8.5.2 Case Temperature
        1. 8.5.2.1 Temperature Calculation
    6. 8.6 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.6.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.6.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.6.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLPC350 System Interfaces
          1. 9.2.2.1.1 Control Interface
          2. 9.2.2.1.2 Input Data Interface
        2. 9.2.2.2 DLPC350 System Output Interfaces
          1. 9.2.2.2.1 Illumination Interface
          2. 9.2.2.2.2 Trigger Interface (Sync Outputs)
        3. 9.2.2.3 DLPC350 System Support Interfaces
          1. 9.2.2.3.1 Reference Clock
          2. 9.2.2.3.2 PLL
          3. 9.2.2.3.3 Program Memory Flash Interface
        4. 9.2.2.4 DMD Interfaces
          1. 9.2.2.4.1 DLPC350 to DMD Digital Data
          2. 9.2.2.4.2 DLPC350 to DMD Control Interface
          3. 9.2.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing Requirements
    2. 10.2 DMD Power Supply Power-Up Procedure
    3. 10.3 DMD Power Supply Power-Down Procedure
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DMD Interface Design Considerations
      2. 11.1.2 DMD Termination Requirements
      3. 11.1.3 Decoupling Capacitors
      4. 11.1.4 Power Plane Recommendations
      5. 11.1.5 Signal Layer Recommendations
      6. 11.1.6 General Handling Guidelines for CMOS-Type Pins
      7. 11.1.7 PCB Manufacturing
        1. 11.1.7.1 General Guidelines
        2. 11.1.7.2 Trace Widths and Minimum Spacings
        3. 11.1.7.3 Routing Constraints
        4. 11.1.7.4 Fiducials
        5. 11.1.7.5 Flex Considerations
        6. 11.1.7.6 DLPC350 Thermal Considerations
    2. 11.2 Layout Example
      1. 11.2.1 Printed Circuit Board Layer Stackup Geometry
      2. 11.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration
      3. 11.2.3 Recommended DLPC350 PLL Layout Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 12.1.2 Device Nomenclature
    2. 12.2 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 接收文档更新通知
    5. 12.5 支持资源
    6.     Trademarks
    7. 12.6 Electrostatic Discharge Caution
    8. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.7 Timing Requirements

Over operating free-air temperature range (unless otherwise noted). This data sheet provides timing at the device pin.

MIN NOM MAX UNIT
tsu(1) Setup time: DATA before rising or falling edge of DCLK (1) 0.7 ns
Setup time: TRC before rising or falling edge of DCLK (1) 0.7
Setup time: SCTRL before rising or falling edge of DCLK (1) 0.7
tsu(2) Setup time: LOADB low before rising edge of DCLK (1) 0.7 ns
tsu(3) Setup time: SAC_BUS low before rising edge of SAC_CLK (1) 1 ns
tsu(4) Setup time: DRC_BUS high before rising edge of SAC_CLK (1) 1 ns
tsu(5) Setup time: DRC_STROBE high before rising edge of SAC_CLK (1) 2 ns
th(1) Hold time: DATA after rising or falling edge of DCLK (1) 0.7 ns
Hold time: TRC after rising or falling edge of DCLK (1) 0.7
Hold time: SCTRL after rising or falling edge of DCLK (1) 0.7
th(2) Hold time: LOADB low after falling edge of DCLK (1) 0.7 ns
th(3) Hold time: SAC_BUS low after rising edge of SAC_CLK (1) 1 ns
th(4) Hold time: DRC_BUS after rising edge of SAC_CLK (1) 1 ns
th(5) Hold time: DRC_STROBE after rising edge of SAC_CLK (1) 2 ns
tr Rise time (20% to 80%): DCLK / SAC_CLK, VREF = 1.8 V 1.08 ns
Rise time (20% to 80%): DATA / TRC / SCTRL / LOADB, VREF = 1.8 V 1.08
tf Fall time (20% to 80%): DCLK / SAC_CLK, VREF = 1.8 V 1.08 ns
Fall time (20% to 80%): DATA / TRC / SCTRL / LOADB 1.08
tc1 Clock cycle: DCLK 8.33 10 12.5 ns
tc3 Clock cycle: SAC_CLK 12.5 13.33 14.3 ns
tw1 Pulse width high or low: DCLK 3.33 ns
tw2 Pulse width low: LOADB 4.73 ns
tw3 Pulse width high or low: SAC_CLK 5 ns
tw5 Pulse width high: DRC_STROBE 7 ns
(1) Setup and hold times shown are for fast input slew rates >1 V/ns. For slow slew rates >0.5 V/ns and <1 V/ns, the setup and hold times are longer. For every 0.1 V/ns decrease in slew rate from 1 V/ns, add 150 ps on setup and hold.
GUID-7813410D-3E00-4FB6-8DD9-7982AD06E39E-low.png Figure 7-2 Timing Diagram
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