ZHCSJA3B January 2019 – May 2022 DLP4500NIR
PRODUCTION DATA
The data interface has two input data ports: a parallel RGB-input port and an FPD-Link LVDS input port. Both input ports can support up to 30 bits and have a nominal I/O voltage of 3.3 V. See the DLPC350 controller data sheet (listed in Section 12.2.1) for details relating to maximum and minimum input timing specifications.
The parallel RGB port can support up to 30 bits in video mode. In pattern mode, only the upper 8 bits of each color are recognized, thereby creating a 24 bit bus from the 30 bit input bus.
The FPD-Link input port can be configured to connect to a video decoder device or an external processor through a 24-, 27-, or 30-bit interface.
Table 9-2 provides a description of the signals associated with the data interface.
| SIGNAL NAME | DESCRIPTION |
|---|---|
| RGB Parallel Interface | |
| P1_(A, B, C)_[0:9] | 30-bit data inputs 10 bits for each of the red, green, and blue channels). If interfacing to a system with less than 10-bits per color, connect the bus of the red, green, and blue channels to the upper bits of the DLPC350 10-bit bus. |
| P1A_CLK | Pixel clock; all input signals on data interface are synchronized with this clock. |
| P1_VSYNC | Vertical sync |
| P1_HSYNC | Horizontal sync |
| P1_DATAEN | Input data valid |
| FPD-Link LVDS Input | |
| RCK | Differential input signal for clock |
| RA_IN | Differential input signal for data channel A |
| RB_IN | Differential input signal for data channel B |
| RC_IN | Differential input signal for data channel C |
| RD_IN | Differential input signal for data channel D |
| RE_IN | Differential input signal for data channel E |
The A, B, and C input data channels of Port 1 can be internally swapped for optimum board layout.