ZHCSRC7C December 2022 – August 2024 DLP4620S-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPD | Output propagation, clock to Q, rising edge of LS_CLK (differential clock signal) input to LS_RDATA output(2) | CL = 45pF | 15 | ns | ||
Slew rate, LS_RDATA | 0.5 | V/ns | ||||
Output duty cycle distortion, LS_RDATA_A and LS_RDATA_B | 40% | 60% |