米6体育平台手机版

ZHCSRC7C December 2022 – August 2024 DLP4620S-Q1

PRODUCTION DATA

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机械数据 (封装 | 引脚)

FQX|120
- MCLG047B

散热焊盘机械数据 (封装 | 引脚)

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5.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device reliability.

		MIN	MAX	UNIT
SUPPLY VOLTAGE
V_DD	Supply voltage for LVCMOS core logic⁽¹⁾ Supply voltage for LPSDR low speed interface	–0.5	2.3	V
V_DDI	Supply voltage for SubLVDS receivers⁽¹⁾	–0.5	2.3	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode ⁽¹⁾⁽²⁾	–0.5	8.75	V
V_BIAS	Supply voltage for micromirror electrode ⁽¹⁾	–0.5	17	V
V_RESET	Supply voltage for micromirror electrode ⁽¹⁾	–11	0.5	V
\|V_DDI– V_DD\|	Supply voltage delta (absolute value) ⁽³⁾		0.3	V
\|V_BIAS– V_OFFSET\|	Supply voltage delta (absolute value) ⁽⁴⁾		8.75	V
\|V_BIAS – V_RESET\|	Supply voltage delta (absolute value) ⁽⁵⁾		28	V
INPUT VOLTAGE
Input voltage for LVCMOS Inputs ⁽¹⁾		–0.5	V_DD + 0.5	V
Input voltage for other inputs SubLVDS ⁽¹⁾⁽⁶⁾		–0.5	V_DDI + 0.5	V
INPUT PINS
\|V_ID\|	SubLVDS input differential voltage (absolute value) ⁽⁶⁾		810	mV
\|I_ID\|	SubLVDS input differential current		10	mA
CLOCK FREQUENCY
F_{max_LS}	Clock frequency for low speed interface LS_CLK	100	130	MHz
TEMPERATURE DIODE
I_{TEMP_DIODE}	Max current source into temperature diode		120	µA
ENVIRONMENTAL
T_ARRAY	Operating DMD array temperature	–40	105	°C

(1) All voltage values are with respect to the ground terminals (V_SS). The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are also required.

(2) V_OFFSET supply transients must fall within specified voltages.

(3) Exceeding the recommended allowable absolute voltage difference between V_DDI and V_DD may result in excessive current draw and permanent damage to the device.

(4) Exceeding the recommended allowable absolute voltage difference between V_BIAS and V_OFFSET may result in excessive current draw and permanent damage to the device.

(5) Exceeding the recommended allowable absolute voltage difference between V_BIAS and V_RESET may result in excessive current draw and permanent damage to the device.

(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential inputs must not exceed the specified limit or damage to the internal termination resistors may result.