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ZHCSRC7C December 2022 – August 2024 DLP4620S-Q1

PRODUCTION DATA

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机械数据 (封装 | 引脚)

FQX|120
- MCLG047B

散热焊盘机械数据 (封装 | 引脚)

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5.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

		MIN	NOM	MAX	UNIT
SUPPLY VOLTAGE
V_DD	Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface	1.65	1.8	1.95	V
V_DDI	Supply voltage for SubLVDS receivers	1.65	1.8	1.95	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode ⁽³⁾	8.25	8.5	8.75	V
V_BIAS	Supply voltage for mirror electrode	15.5	16	16.5	V
V_RESET	Supply voltage for micromirror electrode	–9.5	–10	–10.5	V
\|V_DDI– V_DD\|	Supply voltage delta (absolute value) ⁽⁴⁾			0.3	V
\|V_BIAS– V_OFFSET\|	Supply voltage delta (absolute value) ⁽⁵⁾			8.75	V
\|V_BIAS – V_RESET\|	Supply voltage delta (absolute value) ⁽⁶⁾			28	V
LOW-SPEED LPDSR INTERFACE
f_{clock_LS}	Clock frequency for low speed interface LS_CLK	108		120	MHz
DCD_IN	LSIF duty cycle distortion (LS_CLK)	44%		56%
SUBLVDS INTERFACE
f_{clock_HS}	Clock frequency for high-speed interface DCLK			600	MHz
DCD_IN	LVDS duty cycle distortion (DCLK)	44%		56%
\|V_ID\|	LVDS differential input voltage magnitude ⁽⁷⁾	150	250	350	mV
V_CM	Common mode voltage ⁽⁷⁾	700	900	1100	mV
V_SUBLVDS	SubLVDS voltage ⁽⁷⁾	525		1275	mV
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
Z_IN	Internal differential termination resistance ⁽⁸⁾	80	100	120	Ω
	100Ω differential PCD trace	6.35		152.4	mm
ENVIRONMENTAL
T_ARRAY	Array Temperature ⁽⁹⁾⁽¹¹⁾	-40		105	°C
Illumination
ILL_UV	Illumination, wavelength < 395 nm ⁽¹⁰⁾			2	mW/cm²
ILL_OVERFILL	Illumination overfill maximum heat load in area shown in the Illumination Overfill Diagram			90	mW/mm²

(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(2) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are also required.

(3) V_OFFSET supply transients must fall within specified min/max voltages.

(4) To prevent excess current, the supply voltage delta |V_DDI – V_DD| must be less than the specified limit.

(5) To prevent excess current, the supply voltage delta |V_BIAS – V_OFFSET| must be less than the specified limit.

(6) To prevent excess current, the supply voltage delta |V_BIAS – V_RESET| must be less than the specified limit.

(7) See Figure 5-6 and Figure 5-7.

(8) See Figure 5-8.

(9) DMD Active Array temperature can be calculated as shown in the Micromirror Array Temperature Calculation section.

(10) The maximum operation conditions for operating temperature and UV illumination shall not be implemented simultaneously.

(11) Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested.