米6体育平台手机版

ZHCSRE5B December 2022 – August 2024 DLP4621-Q1

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

5.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted

			MIN	NOM	MAX	UNIT
Low-Speed Interface
t_r	Rise slew rate ⁽¹⁾⁽²⁾	(20% to 80%) × VDD	0.25			V/ns
t_f	Fall slew rate ⁽¹⁾⁽²⁾	(80% to 20%) × VDD	0.25			V/ns
t_c	Cycle time LS_CLK		7.7	8.3		ns
t_W(H)	Pulse duration LS_CLK high⁽³⁾	50% to 50% reference points	3.1			ns
t_W(L)	Pulse duration LS_CLK low⁽³⁾	50% to 50% reference points	3.1			ns
t_su	Setup time⁽³⁾	LS_WDATA valid before LS_CLK↑ or LS_CLK↓	1.5			ns
t_h	Hold time⁽³⁾	LS_WDATA valid after LS_CLK↑ or LS_CLK↓	1.5			ns
t_WINDOW	Window time	Setup time + hold time	3			ns
t_DERATING	Window time derating	For each 0.25 V/ns reduction in slew rate below 1 V/ns		0.35		ns
High-Speed Interface
t_r	Rise slew rate⁽²⁾	20% to 80% reference points	0.7	1		V/ns
t_f	Fall slew rate⁽²⁾	80% to 20% reference points	0.7	1		V/ns
t_c	Cycle time DCLK ⁽³⁾		1.61	1.67		ns
t_W(H)	Pulse duration DCLK high⁽³⁾	50% to 50% reference points	0.75			ns
t_W(L)	Pulse duration DCLK low⁽³⁾	50% to 50% reference points	0.75			ns
t_WINDOW	Window time⁽³⁾⁽⁴⁾	Setup time + Hold time	0.3			ns
t_{LVDS-EN+REFGEN}	Power-up receiver ⁽⁵⁾				2000	ns

(1) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-2.

(5) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.