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ZHCSLB6C may 2020 – july 2023 DLP4710LC

PRODUCTION DATA

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机械数据 (封装 | 引脚)

FQL|100
- MCLG032C

散热焊盘机械数据 (封装 | 引脚)

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6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾ ⁽³⁾

		MIN	NOM	MAX	UNIT
SUPPLY VOLTAGE RANGE⁽⁴⁾
V_DD	Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface	1.7	1.8	1.95	V
V_DDI	Supply voltage for SubLVDS receivers	1.7	1.8	1.95	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode⁽⁵⁾	9.5	10	10.5	V
V_BIAS	Supply voltage for mirror electrode	17.5	18	18.5	V
V_RESET	Supply voltage for micromirror electrode	–14.5	–14	–13.5	V
\|V_DDI–V_DD\|	Supply voltage delta (absolute value)⁽⁶⁾			0.3	V
\|V_BIAS–V_OFFSET\|	Supply voltage delta (absolute value)⁽⁷⁾			10.5	V
\|V_BIAS–V_RESET\|	Supply voltage delta (absolute value)⁽⁸⁾			33	V
CLOCK FREQUENCY
ƒ_clock	Clock frequency for low speed interface LS_CLK⁽⁹⁾	108		120	MHz
ƒ_clock	Clock frequency for high speed interface DCLK⁽¹⁰⁾	300		540	MHz
	Duty cycle distortion DCLK	44%		56%
SUBLVDS INTERFACE⁽¹⁰⁾
\| V_ID \|	SubLVDS input differential voltage (absolute value) Figure 6-9, Figure 6-10	150	250	350	mV
V_CM	Common mode voltage Figure 6-9, Figure 6-10	700	900	1100	mV
V_SUBLVDS	SubLVDS voltage Figure 6-9, Figure 6-10	575		1225	mV
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
Z_IN	Internal differential termination resistance Figure 6-11	80	100	120	Ω
	100-Ω differential PCB trace	6.35		152.4	mm
ENVIRONMENTAL
T_ARRAY	Array Temperature – long-term operational⁽¹¹⁾⁽¹²⁾⁽¹³⁾⁽¹⁴⁾	0		40 to 70⁽¹³⁾	°C
	Array Temperature - short-term operational, 25 hr max⁽¹²⁾⁽¹⁵⁾	–20		-10
	Array Temperature - short-term operational, 500 hr max⁽¹²⁾⁽¹⁵⁾	–10		0
	Array Temperature – short-term operational, 500 hr max⁽¹²⁾⁽¹⁵⁾	70		75
\|T_DELTA\|	Absolute Temperature difference between any point on the window edge and the ceramic test point TP1 ⁽¹⁶⁾			15	°C
T_WINDOW	Window Temperature – operational⁽¹¹⁾ ⁽¹⁷⁾			90	°C
T_DP-AVG	Average dew point temperature (non-condensing)⁽¹⁸⁾			24	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽¹⁹⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			6	Months
ILLUMINATION
ILL_UV	Illumination power at wavelengths < 410 nm⁽¹¹⁾			10	mW/cm²
ILL_VIS	Illumination power at wavelengths ≥ 410 nm and ≤ 800 nm⁽²¹⁾			20.5	W/cm²
ILL_IR	Illumination power at wavelengths > 800 nm			10	mW/cm²
ILL_BLU	Illumination power at wavelengths ≥ 410 nm and ≤ 475 nm⁽²¹⁾			6.5	W/cm²
ILL_BLU1	Illumination power at wavelengths ≥ 410 nm and ≤ 445 nm⁽²¹⁾			1.2	W/cm2
ILL_θ	Illumination marginal ray angle⁽²⁰⁾			55	deg

(1) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.

(2) Recommended Operating ConditionsRecommended Operating ConditionsRecommended Operating ConditionsRecommended Operating Conditions are applicable after the DMD is installed in the final product.

(3) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating ConditionsRecommended Operating ConditionsRecommended Operating ConditionsRecommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating ConditionsRecommended Operating ConditionsRecommended Operating ConditionsRecommended Operating Conditions limits.

(4) All voltage values are with respect to the ground pins (VSS).

(5) VOFFSET supply transients must fall within specified max voltages.

(6) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(7) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(8) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit.

(9) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(10) Refer to the SubLVDS timing requirements in Section 6.7.

(11) Simultaneous exposure of the DMD to the maximum Recommended Operating ConditionsRecommended Operating ConditionsRecommended Operating ConditionsRecommended Operating Conditions for temperature and UV illumination will reduce device lifetime.

(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-1 and the Package Thermal Resistance using Section 7.6.

(13) Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 7.8 for a definition of micromirror landed duty cycle.

(14) Long-term is defined as the usable life of the device

(15) Short-term is the total cumulative time over the useful life of the device.

(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(17) Window temperature is the highest temperature on the window edge shown in Figure 7-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.

(18) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CT_ELR.

(20) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.

(21) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (T_ARRAY).

Figure 6-1 Max Recommended Array Temperature – Derating Curve