米6体育平台手机版

ZHCSO64B September 2020 – April 2022 DLP471TE

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

FYN|149
- MCCC007A

散热焊盘机械数据 (封装 | 引脚)

订购信息

zhcso64b_pm

10.6 Trace Length Matching Recommendations

Table 10-4 and Table 10-5 describe recommended signal trace length matching requirements. Follow these guidelines to avoid routing long traces over large areas of the PCB:

Match the trace lengths so that longer signals route in a serpentine pattern
Minimize the number of turns.
Ensure that the turn angles no sharper than 45 degrees.

Figure 10-1 shows an example of the HSSI signal pair routing.

Signals listed in Table 10-4 are specified fro data rate operation at up to 3.2 Gbps. Minimize the layer changes for these signals. Minimize the number of vias. Avoid sharp turns and layer switching while minimizing the lengths. When layer changes are necessary, place GND vias around the signal vias to provide a signal return path. The distance from one pair of differential signals to another must be at least 2 times the distance within the pair.

Table 10-4 HSSI High Speed DMD Data Signals

SIGNAL NAME	REFERENCE SIGNAL	ROUTING SPECIFICATION	UNIT
DMD_HSSI0_N(0...7), DMD_HSSI0_P(0...7)	DMD_HSSI0_CLK_N, DMD_HSSI_CLK_P	±0.25	inch
DMD_HSSI1_N(0...7), DMD_HSSI1_P(0...7)	DMD_HSSI0_CLK_N, DMD_HSSI_CLK_P	±0.25	inch
DMD_HSSI0_CLK_P	DMD_HSSI1_CLK_P	±0.05	inch
Intra-pair P	Intra-pair N	±0.01	inch

Table 10-5 Other Timing Critical Signals

SIGNAL NAME	Constraints	Routing Layers
LS_CLK_P, LS_CLK_N LS_WDATA_P, LS_WDATA_N LS_RDATA_A	Intra-pair (P to N) Matched to 0.01 inches Signal-to-signal Matched to +/- 0.25 inches	Layers 3, 8

Figure 10-1 Example HSSI PCB Routing