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ZHCSNH4B august 2020 – july 2023 DLP471TP

PRODUCTION DATA

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机械数据 (封装 | 引脚)

FQQ|270
- MCLG038A

散热焊盘机械数据 (封装 | 引脚)

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9.2 DMD Power Supply Power-Down Procedure

During power-down, V_DD and V_DDA must be supplied until after V_BIAS, V_RESET, and V_OFFSET are discharged to within the specified limit of ground. See Table 9-2.
During power-down, it is a strict requirement that the voltage difference between V_BIAS and V_OFFSET must be within the specified limit shown in Section 6.4.
During power-down, there is no requirement for the relative timing of V_RESET with respect to V_BIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, in Section 6.4, and in Figure 9-1.
During power-down, LVCMOS input pins must be less than specified in Section 6.4.

A. See Section 5 for the Pin Functions Table.

B. To prevent excess current, the supply voltage difference |V_OFFSET – V_BIAS| must be less than the specified limit in Section 6.4.

C. To prevent excess current, the supply difference |V_BIAS – V_RESET| must be less than the specified limit in Section 6.4.

D. V_BIAS should power up after V_OFFSET has powered up, per the Delay1 specification in Table 9-2.

E. DLP controller software initiates the global V_BIAS command.

F. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates DMD_EN_ARSTZ and disables V_BIAS, V_RESET, and V_OFFSET.

G. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware DMD_EN_ARSTZ will go low.

H. V_DD must remain high until after V_OFFSET, V_BIAS, V_RESET go low, per Delay2 specification in Table 9-2.

I. To prevent excess current, the supply voltage delta |V_DDA – V_DD| must be less than specified limit in Section 6.4.

Figure 9-1 DMD Power Supply Requirements

Table 9-2 DMD Power-Supply Requirements

PARAMETER	DESCRIPTION	MIN	NOM	MAX	UNIT
Delay1⁽¹⁾	Delay from V_OFFSET settled at recommended operating voltage to V_BIAS and V_RESET power up	1	2		ms
Delay2⁽¹⁾	Delay V_DD must be held high from V_OFFSET, V_BIAS and V_RESET powering down.	50			us

(1) See Figure 9-1.