ZHCSKV7A November   2020  – July 2022 DLP500YX

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics
    10. 6.10 System Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Window Characteristics
    14. 6.14 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Micromirror Array Temperature Calculation using Illumination Power Density
      2. 7.6.2 Micromirror Array Temperature Calculation using Total Illumination Power
      3. 7.6.3 Micromirror Array Temperature Calculation using Screen Lumens
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 DMD Die Temperature Sensing
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Restrictions on Hot Plugging and Hot Swapping
      1. 9.3.1 No Hot Plugging
      2. 9.3.2 No Hot Swapping
      3. 9.3.3 Intermittent or Voltage Power Spike Avoidance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Critical Signal Guidelines
      2. 10.1.2 Power Connection Guidelines
      3. 10.1.3 Noise Coupling Avoidance
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 第三方米6体育平台手机版_好二三四免责声明
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

5 Pin Configuration and Functions

GUID-20200729-CA0I-WVNX-L1ZN-7KZCHFTHC4KK-low.pngFigure 5-1 FXK Package257-Pin CLGABottom View
CAUTION:

To ensure reliable, long-term operation of the DLP500YX DMD, it is critical to properly manage the layout and operation of the signals identified in Table 5-1. For specific details and guidelines, refer to Section 10.1 section before designing the board.

Table 5-1 Pin Functions
PIN TYPE(2) SIGNAL DATA
RATE(6)		 INTERNAL
TERMINATION(7)		 DESCRIPTION(1) TRACE
LENGTH
(mil(8))
NAME NO.
D_AN(0) C6 Input LVDS DDR Differential Data negative 805
D_AN(1) C3
D_AN(2) E1
D_AN(3) C4
D_AN(4) D1
D_AN(5) B8
D_AN(6) F4
D_AN(7) E3
D_AN(8) C11
D_AN(9) F3
D_AN(10) K4
D_AN(11) H3
D_AN(12) J3
D_AN(13) C13
D_AN(14) A5
D_AN(15) A3
D_AP(0) C7 Input LVDS DDR Differential Data positive 805
D_AP(1) C2
D_AP(2) E2
D_AP(3) B4
D_AP(4) C1
D_AP(5) B7
D_AP(6) E4
D_AP(7) D3
D_AP(8) C12
D_AP(9) F2
D_AP(10) J4
D_AP(11) G3
D_AP(12) J2
D_AP(13) C14
D_AP(14) A6
D_AP(15) A4
D_BN(0) N4 Input LVDS DDR Differential Data negative 805
D_BN(1) Z11
D_BN(2) W4
D_BN(3) W10
D_BN(4) L1
D_BN(5) V8
D_BN(6) W6
D_BN(7) M1
D_BN(8) R4
D_BN(9) W1
D_BN(10) U4
D_BN(11) V2
D_BN(12) Z5
D_BN(13) N3
D_BN(14) Z2
D_BN(15) L4
D_BP(0) M4 Input LVDS DDR Differential Data positive 805
D_BP(1) Z12
D_BP(2) Z4
D_BP(3) Z10
D_BP(4) L2
D_BP(5) V9
D_BP(6) W7
D_BP(7) N1
D_BP(8) P4
D_BP(9) V1
D_BP(10) T4
D_BP(11) V3
D_BP(12) Z6
D_BP(13) N2
D_BP(14) Z3
D_BP(15) L3
D_CN(0) H27 Input LVDS DDR Differential Data negative 805
D_CN(1) A20
D_CN(2) H28
D_CN(3) K28
D_CN(4) K30
D_CN(5) C23
D_CN(6) G27
D_CN(7) J30
D_CN(8) B24
D_CN(9) A21
D_CN(10) A27
D_CN(11) C29
D_CN(12) A26
D_CN(13) C25
D_CN(14) A29
D_CN(15) C30
D_CP(0) J27 Input LVDS DDR Differential Data positive 805
D_CP(1) A19
D_CP(2) H29
D_CP(3) K27
D_CP(4) K29
D_CP(5) C22
D_CP(6) F27
D_CP(7) H30
D_CP(8) B25
D_CP(9) B21
D_CP(10) B27
D_CP(11) C28
D_CP(12) A25
D_CP(13) C24
D_CP(14) A28
D_CP(15) B30
D_DN(0) V25 Input LVDS DDR Differential Data negative 805
D_DN(1) V28
D_DN(2) T30
D_DN(3) V27
D_DN(4) U30
D_DN(5) W23
D_DN(6) R27
D_DN(7) T28
D_DN(8) V20
D_DN(9) R28
D_DN(10) L27
D_DN(11) N28
D_DN(12) M28
D_DN(13) V18
D_DN(14) Z26
D_DN(15) Z28
D_DP(0) V24 Input LVDS DDR Differential Data positive 805
D_DP(1) V29
D_DP(2) T29
D_DP(3) W27
D_DP(4) V30
D_DP(5) W24
D_DP(6) T27
D_DP(7) U28
D_DP(8) V19
D_DP(9) R29
D_DP(10) M27
D_DP(11) P28
D_DP(12) M29
D_DP(13) V17
D_DP(14) Z25
D_DP(15) Z27
SCTRL_AN G1 Input LVDS DDR Differential Serial control negative(3) 805
SCTRL_AP F1 Input LVDS DDR Differential Serial control positive(3) 805
SCTRL_BN V5 Input LVDS DDR Differential Serial control negative(3) 805
SCTRL_BP V4 Input LVDS DDR Differential Serial control positive(3) 805
SCTRL_CN C26 Input LVDS DDR Differential Serial control negative(3) 805
SCTRL_CP C27 Input LVDS DDR Differential Serial control positive(3) 805
SCTRL_DN P30 Input LVDS DDR Differential Serial control negative(3) 805
SCTRL_DP R30 Input LVDS DDR Differential Serial control positive(3) 805
DCLK_AN H2 Input LVDS Differential Clock negative(3) 805
DCLK_AP H1 Input LVDS Differential Clock positive(3) 805
DCLK_BN V6 Input LVDS Differential Clock negative(3) 805
DCLK_BP V7 Input LVDS Differential Clock positive(3) 805
DCLK_CN D27 Input LVDS Differential Clock negative(3) 805
DCLK_CP E27 Input LVDS Differential Clock positive(3) 805
DCLK_DN N29 Input LVDS Differential Clock negative(3) 805
DCLK_DP N30 Input LVDS Differential Clock positive(3) 805
SCPCLK A10 Input LVCMOS Pull down Serial communications port clock. Active only when SCPENZ is logic low(3)
SCPDI A12 Input LVCMOS SDR Pull down Serial communications port data input. Synchronous to SCPCLK rising edge(3)
SCPENZ C10 Input LVCMOS Pull down Serial communications port enable active low(3)
SCPDO A11 Output LVCMOS SDR Serial communications port output
RESET_ADDR(0) Z13 Input LVCMOS Pull down Reset driver address select(3)
RESET_ADDR(1) W13
RESET_ADDR(2) V10
RESET_ADDR(3) W14
RESET_MODE(0) W9 Input LVCMOS Pull down Reset driver mode select(3)
RESET_SEL(0) V14 Reset driver level select(3)
RESET_SEL(1) Z8 Reset driver level select.(3)
RESET_STROBE Z9 Input LVCMOS Pull down Rising edge latches in RESET_ADDR, RESET_MODE, & RESET_SEL.(3)
PWRDNZ A8 Input LVCMOS Pull down Active low device reset.(3)
RESET_OEZ W15 Input LVCMOS Pull up Active low output enable for internal reset driver circuits.(3)
RESET_IRQZ V16 Output LVCMOS Active low output interrupt to DLP controller
EN_OFFSET C9 Output LVCMOS Active high enable for external VOFFSET regulator
PG_OFFSET A9 Input LVCMOS Pull up Active low fault from external VOFFSET regulator(3)
TEMP_N B18

Input

 Analog Temperature sensor diode cathode
TEMP_P B17

Input

 Analog Temperature sensor diode anode
RESERVED **MUST VERIFY WITH SRC DATA SHEET D12, D13, D14, D15, D16, D17, D18, D19, U12, U13, U14, U15 NC Analog Pull Down Do not connect on DLP system board. No connect. No electrical connections from CMOS bond pad to package pin.
No Connect U16, U17, U18, U19 NC No connect. No electrical connection from CMOS bond pad to package pin
RESERVED_BA W11 Output LVCMOS Do not connect on DLP system board.
RESERVED_BB B11
RESERVED_BC Z20
RESERVED_BD C18
RESERVED_PFE A18 Input LVCMOS Pull down Do not connect on DLP system board.
RESERVED_TM C8
RESERVED_TP0 Z19 Input Analog Do not connect on DLP system board.
RESERVED_TP1 W20
RESERVED_TP2 W19
VBIAS(4) C15, C16, V11, V12 Power Analog Supply voltage for positive bias level of micromirror reset signal
VRESET(4) G4, H4, J1, K1 Power Analog Supply voltage for negative reset level of micromirror reset signal
VOFFSET(4) A30, B2, M30, Z1, Z30 Power Analog Supply voltage for HVCMOS logic. Supply voltage for positive offset level of micromirror reset signal. Supply voltage for stepped high voltage at micromirror address electrodes
VCC(4) A24, A7, B10, B13, B16, B19, B22, B28, B5, C17, C20, D4, J29, K2, L29, M2, N27, U27, V13, V15, V22, W17, W21, W26, W29, W3, Z18, Z23, Z29, Z7 Power Analog Supply voltage for LVCMOS core. Supply voltage for positive offset level of micromirror reset signal during power down. Supply voltage for normal high level at micromirror address electrodes
VSS(5) A13, A22, A23, B12, B14, B15, B20, B23, B26, B29, B3, B6, B9, C19, C21, C5, D2, G2, J28, K3, L28, L30, M3, P27, P29, U29, V21, V23, V26, W12, W16, W18, W2, W22, W25, W28, W30, W5, W8, Z21, Z22, Z24 Ground Device ground. Common return for all power.
(1) The DLP500YX DMD is a component of a DLP chipset. Reliable function and operation of the DLP500YX DMD requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP DMD.
(2) I = Input, O = Output, P = Power, G = Ground, NC = No connect
(3) These signals are very sensitive to noise or intermittent power connections, which can cause irreversible DMD micromirror array damage or, to a lesser extent, image disruption. Consider this precaution during DMD board design and manufacturer handling of the DMD sub-assemblies.
(4) The following power supplies are required to operate the DMD: VCC, VOFFSET, VBIAS, and VRESET.
(5) VSS must be connected for proper DMD operation.
(6) DDR = Double Data Rate, SDR = Single Data Rate. Refer to the Timing Requirements for specifications and relationships.
(7) Internal term = CMOS level internal termination. Refer to Recommended Operating Conditions for differential termination specification.
(8) Dielectric Constant for the DMD FXK (S410) ceramic package is approximately 9.6. For the package trace lengths shown: Propagation Speed = 11.8 sqrt (9.60 = 3.808 in/ns. Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm.
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