ZHCSN33B November 2017 – February 2023 DLP550JE
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 Storage Conditions
- 6.3 ESD Ratings
- 6.4 Recommended Operating Conditions
- 6.5 Thermal Information
- 6.6 Electrical Characteristics
- 6.7 Timing Requirements
- 6.8 Window Characteristics
- 6.9 System Mounting Interface Loads
- 6.10 Micromirror Array Physical Characteristics
- 6.11 Micromirror Array Optical Characteristics
- 6.12 Chipset Component Usage Specification
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VOLTAGE SUPPLY | |||||
| VCC | Supply voltage for LVCMOS core logic#DLPS1013784 | 3.0 | 3.3 | 3.6 | V |
| VCCI | Supply voltage for LVDS receivers#DLPS1013784 | 3.0 | 3.3 | 3.6 | V |
| VOFFSET | Mirror Electrode and HVCMOS voltage#DLPS1013784#DLPS1018910 | 8.25 | 8.5 | 8.75 | V |
| VMBRST | Micromirror clocking pulse voltages#DLPS1013784 | –27 | 26.5 | V | |
| |VCCI–VCC| | Supply voltage delta (absolute value)#DLPS1019220 | 0.3 | V | ||
| LVCMOS INTERFACE | |||||
| VIH | High level input voltage | 1.7 | 2.5 | VCC + 0.3 | V |
| VIL | Low level input voltage | –0.3 | 0.7 | V | |
| IOH | High level output current at VOH = 2.4 V | –20 | mA | ||
| IOL | Low level output current at VOL = 0.4 V | 15 | mA | ||
| tPWRDNZ | PWRDNZ pulse width#DLPS1012054 | 10 | ns | ||
| SCP INTERFACE | |||||
| fSCPCLK | SCP clock frequency#T4989946-5 | 50 | 500 | kHz | |
| tSCP_PD | Propagation delay, clock to Q, from rising-edge of SCPCLK to valid SCPDO#T4989946-20 | 0 | 900 | ns | |
| tSCP_DS | SCPDI clock setup time (before SCPCLK falling-edge)#T4989946-20 | 800 | ns | ||
| tSCP_DH | SCPDI hold time (after SCPCLK falling-edge)#T4989946-20 | 900 | |||
| tSCP_NEG_ENZ | Time between falling-edge of SCPENZ and the first rising-edge of SCPCLK | 1 | us | ||
| tSCP_POS_ENZ | Time between falling-edge of SCPCLK and the rising-edge of SCPENZ | 1 | us | ||
| tSCP_PW_ENZ | SCPENZ inactive pulse width (high level) | 1 | 1/fSCPCLK | ||
| tr_SCP | Rise time for SCP signals | 200 | ns | ||
| tfP | Fall time for SCP signals | 200 | ns | ||
| LVDS INTERFACE | |||||
| fCLOCK | Clock frequency for LVDS interface (all channels), DCLK#T4989946-34 | 320 | 330 | MHz | |
| |VID| | Input differential voltage (absolute difference)#T4989946-21 | 100 | 400 | 600 | mV |
| VCM | Common mode voltage#T4989946-21 | 1200 | mV | ||
| VLVDS | LVDS voltage#T4989946-21 | 0 | 2000 | mV | |
| tr | Rise time (20% to 80%) | 100 | 400 | ps | |
| tr | Fall time (80% to 20%) | 100 | 400 | ps | |
| tLVDS_RSTZ | Time required for LVDS receivers to recover from PWRDNZ | 10 | ns | ||
| ZIN | Internal differential termination resistance | 95 | 105 | Ω | |
| ENVIRONMENTAL | |||||
| TARRAY | Array temperature, long-term operational#DLPS1014991 #DLPS1018123 #T4989946-18 | 10 | 40 to 70#T4989946-1 | °C | |
| Array temperature, short-term operational#DLPS1018123#T4989946-19 | 0 | 10 | °C | ||
| TWINDOW | Window temperature – operational#DLPS1016301 | 85 | °C | ||
| T|DELTA | | Absolute temperature delta between any point on the window edge and the ceramic test point TP1#T4989946-22 | 26 | °C | ||
| TDP-AVG | Average dew point temperature (non-condensing)#DLPS1019398 | 28 | °C | ||
| TDP-ELR | Elevated dew point temperature range (non-condensing)#DLPS1013697 | 28 | 36 | °C | |
| CTELR | Cumulative time in elevated dew point temperature range | 24 | Months | ||
| ILLUV | Illumination wavelengths < 395 nm#DLPS1014991 | 0.68 | 2.00 | mW/cm2 | |
| ILLVIS | Illumination wavelengths between 395 nm and 800 nm | Thermally limited | mW/cm2 | ||
| ILLIR | Illumination wavelengths > 800 nm | 10 | mW/cm2 | ||
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage delta |VCCI –
VCC| must be less than specified limit. See GUID-783C8A87-C319-45F0-8ED5-D542F5788D8C.html#GUID-783C8A87-C319-45F0-8ED5-D542F5788D8C.
(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input
pin overrides SCPENZ input pin and tristates the SCPDO output pin.
(5) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(7) See LVDS Timing Requirements in GUID-99C25A6A-6E1F-4AA2-94E4-BF3E57D3C09A.html#GUID-99C25A6A-6E1F-4AA2-94E4-BF3E57D3C09A and GUID-99C25A6A-6E1F-4AA2-94E4-BF3E57D3C09A.html#DLPS0952F2.
(8) Refer to GUID-99C25A6A-6E1F-4AA2-94E4-BF3E57D3C09A.html#DLPS1013519, GUID-99C25A6A-6E1F-4AA2-94E4-BF3E57D3C09A.html#DLPS0952F2J3, and GUID-99C25A6A-6E1F-4AA2-94E4-BF3E57D3C09A.html#DLPS1018371.
(9) Simultaneous exposure of the DMD to the maximum #GUID-4099E5F6-AAA6-418E-9C70-AB9F6B9ED0B7 for temperature and UV illumination reduces device lifetime.
(10) The array temperature cannot be measured directly and must be computed
analytically from the temperature measured at test point 1 (TP1) shown in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477 and the package
thermal
resistance
using the
calculation in
GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.
(11) Long-term is defined as the average over the usable life.
(12) Per #DLPS1019579, the maximum operational array temperature should be derated based on the
micromirror landed duty cycle that the DMD experiences in the end application.
See GUID-1F08C864-8C95-4839-BD9C-1764F1533D8C.html#GUID-1F08C864-8C95-4839-BD9C-1764F1533D8C
for a definition of micromirror landed duty cycle.
(13) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (for example, power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.
(14) The locations of thermal test points TP2, TP3, TP4, and TP5 in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(15) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477. The window test points TP2, TP3, TP4, and TP5 shown in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477 are intended to result in the worst-case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.
(16) The average over time (including storage and operating) that the device is not
in the
"elevated
dew point temperature range."
(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR.
Figure 6-1 Maximum Recommended DMD
Temperature—Derating
Curve