6.1 Absolute Maximum Ratings
see (1)
|
MIN |
MAX |
UNIT |
| SUPPLY VOLTAGE |
| VDD |
Supply voltage for LVCMOS core logic(2)
Supply voltage for LPSDR low speed interface |
–0.5 |
2.3 |
V |
| VDDI |
Supply voltage for SubLVDS receivers(2) |
–0.5 |
2.3 |
V |
| VOFFSET |
Supply voltage for HVCMOS and micromirror electrode(2)(3) |
–0.5 |
8.75 |
V |
| VBIAS |
Supply voltage for micromirror electrode(2) |
–0.5 |
17 |
V |
| VRESET |
Supply voltage for micromirror electrode(2) |
–11 |
0.5 |
V |
| | VDDI–VDD | |
Supply voltage delta (absolute value)(4) |
|
0.3 |
V |
| | VBIAS–VOFFSET | |
Supply voltage delta (absolute value)(5) |
|
8.75 |
V |
| | VBIAS–VRESET | |
Supply voltage delta (absolute value)(6) |
|
28 |
V |
| INPUT VOLTAGE |
| Input voltage for other inputs LPSDR(2) |
–0.5 |
VDD + 0.5 |
V |
| Input voltage for other inputs SubLVDS(2)(7) |
–0.5 |
VDDI + 0.5 |
V |
| INPUT PINS |
| | VID | |
SubLVDS input differential voltage (absolute value)(7) |
|
810 |
mV |
| IID |
SubLVDS input differential current |
|
10 |
mA |
| CLOCK FREQUENCY |
| ƒclock |
Clock frequency for low speed interface LS_CLK |
|
130 |
MHz |
| ƒclock |
Clock frequency for high speed interface DCLK |
|
620 |
MHz |
| ENVIRONMENTAL |
| TARRAY |
Operating DMD array temperature
(Monitored by TMP411 via DLPC230-Q1)(8) |
–40 |
105 |
°C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential inputs must not exceed the specified limit or damage to the internal termination resistors may result.