米6体育平台手机版

ZHCSPA1 February 2022 DLP5531A-Q1

PRODUCTION DATA

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	NOM	MAX	UNIT
SUPPLY VOLTAGE RANGE
VDD	Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface	1.7	1.8	1.95	V
VDDI	Supply voltage for SubLVDS receivers	1.7	1.8	1.95	V
VOFFSET	Supply voltage for HVCMOS and micromirror electrode	8.25	8.5	8.75	V
VBIAS	Supply voltage for mirror electrode	15.5	16	16.5	V
VRESET	Supply voltage for micromirror electrode	–9.5	–10	–10.5	V
\| VDDI–VDD \|	Supply voltage delta (absolute value)			0.3	V
\| VBIAS–VOFFSET \|	Supply voltage delta (absolute value)			8.75	V
CLOCK FREQUENCY
ƒ_max	Clock frequency for low speed interface LS_CLK			120	MHz
ƒ_max	Clock frequency for high speed interface DCLK			600	MHz
	Duty cycle distortion DCLK	44%		56%
SUBLVDS INTERFACE
\| V_ID \|	SubLVDS input differential voltage (absolute value)⁽²⁾	150	250	350	mV
V_CM	Common mode voltage ⁽²⁾	700	900	1100	mV
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
Z_IN	Internal differential termination resistance⁽³⁾	80	100	120	Ω
ENVIRONMENTAL
T_ARRAY	Operating DMD array temperature⁽⁵⁾	–40		105	°C
ILL_UV	Illumination, wavelength < 395 nm ⁽⁴⁾			2	mW/cm ²
ILL_OVERFILL	Illumination overfill maximum heat load in area shown in Figure 6-1			28	mW/mm ²

(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(4) The maximum operation conditions for operating temperature and UV illumination shall not be implemented simultaneously.

(5) Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested.