米6体育平台手机版

ZHCSK93 September 2019 DLP5534-Q1

ADVANCE INFORMATION for pre-production products; subject to change without notice.

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted

			MIN	NOM	MAX	UNIT
LPSDR
t_r	Rise slew rate⁽¹⁾	(20% to 80%) × VDD, see Figure 2	0.25			V/ns
t_ƒ	Fall slew rate⁽¹⁾	(80% to 20%) × VDD, see Figure 2	0.25			V/ns
t_W(H)	Pulse duration LS_CLK high	50% to 50% reference points, see Figure 4	0.75			ns
t_W(L)	Pulse duration LS_CLK low	50% to 50% reference points, see Figure 4	0.75			ns
t_su	Setup time	LS_WDATA valid before LS_CLK ↑ or LS_CLK ↓, see Figure 4	1.5			ns
t_h	Hold time	LS_WDATA valid after LS_CLK ↑ or LS_CLK ↓, see Figure 4	1.5			ns
SubLVDS
t_r	Rise slew rate	20% to 80% reference points, see Figure 3	0.7	1		V/ns
t_ƒ	Fall slew rate	80% to 20% reference points, see Figure 3	0.7	1		V/ns
t_c	Cycle time DCLK	See Figure 4	1.61	1.67		ns
t_W(H)	Pulse duration DCLK high	50% to 50% reference points, see Figure 4	0.75			ns
t_W(L)	Pulse duration DCLK low	50% to 50% reference points, see Figure 4	0.75			ns
t_WINDOW	Window time	Setup time + Hold time, see Figure 4, Figure 5	0.3			ns
t_{LVDS-ENABLE+REFGEN}	Power-up receiver⁽²⁾				2000	ns

(1) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 2.

(2) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

Figure 2. LPSDR Input Rise and Fall Slew Rate

Figure 3. SubLVDS Input Rise and Fall Slew Rate

Figure 4. SubLVDS Switching Parameters

Figure 5. High-Speed Training Scan Window

Figure 6. SubLVDS Voltage Parameters

Figure 7. SubLVDS Waveform Parameters

Figure 8. SubLVDS Equivalent Input Circuit

Figure 9. LPSDR Input Hysteresis