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ZHCSN34A November 2017 – February 2023 DLP650LE

PRODUCTION DATA

9.2 DMD Power Supply Power-Down Procedure

During power-down, V_CC and V_CCI must be supplied until after V_BIAS, V_RESET, and V_OFFSET are discharged to within the specified limit of ground. See Table 9-2.
During power-down, it is a strict requirement that the voltage delta between V_BIAS and V_OFFSET must be within the specified limit shown in Section 6.4.
During power-down, there is no requirement for the relative timing of V_RESET with respect to V_BIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, in Section 6.4, and in Figure 9-1.
During power-down, LVCMOS input pins must be less than specified in Section 6.4.

Table 9-1 DMD Power Supply Transition Points

TIME	DESCRIPTION
t1	DLP controller software enables the DMD power supplies to turn on after RESET_OEZ is at logic high
t1	PG_OFFSET turns OFF after EN_OFFSET turns OFF per the t_D2 specification in Table 9-2.
t2	DLP controller software initiates the global V_BIAS command.
t3	After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates PWRDNZ and disables V_BIAS, V_RESET and V_OFFSET.
t4	Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware, EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal should go high prior to PG_OFFSET turning off to indicate the DMD micromirror has completed the emergency park procedures.

Not to scale. Some details omitted for clarity. See Section 6.4 for all specified limits and Section 5 table for pin descriptions.
To prevent excess current, the supply voltage difference |V_CCI – V_CC| must be less than the specified limit.
To prevent excess current, the supply voltage difference |V_BIAS – V_OFFSET| must be less than the specified limit.
To prevent excess current, the supply voltage difference |V_BIAS – V_RESET| must be less than the specified limit.
See Table 9-2 for delay time descriptions.
See Table 9-1 for transition time point descriptions.

Figure 9-1 Power Supply Timing⁽¹⁾

Table 9-2 Delay Times Requirements

DELAY TIME	DESCRIPTION	MIN	NOM	MAX	UNIT
t_D1	Delay time period from V_OFFSET settled at recommended operating voltage to V_BIAS and V_RESET power up.	1	2		ms
t_D2	Delay time period between PG_OFFSET hold time and when EN_OFFSET goes low	100			ns