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ZHCSN34A November 2017 – February 2023 DLP650LE

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机械数据 (封装 | 引脚)

FYL|149
- MCLG035

散热焊盘机械数据 (封装 | 引脚)

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zhcsn34a_oa

6.8 Timing Requirements

Over Section 6.4 (unless otherwise noted).

PARAMETER DESCRIPTION		SIGNAL	MIN	TYP	MAX	UNIT
LVDS⁽¹⁾
t_C	Clock cycle duration for DCLK_A	LVDS	3.03			ns
t_C	Clock cycle duration for DCLK_B	LVDS	3.03			ns
t_W	Pulse duration for DCLK_A	LVDS	1.36	1.52		ns
t_W	Pulse duration for DCLK_B	LVDS	1.36	1.52		ns
t_SU	Setup time for D_A(15:0) before DCLK_A	LVDS	0.35			ns
t_SU	Setup time for D_A(15:0) before DCLK_B	LVDS	0.35			ns
t_SU	Setup time for SCTRL_A before DCLK_A	LVDS	0.35			ns
t_SU	Setup time for SCTRL_B before DCLK_B	LVDS	0.35			ns
t_H	Hold time for D_A(15:0) after DCLK_A	LVDS	0.35			ns
t_H	Hold time for D_B(15:0) after DCLK_B	LVDS	0.35			ns
t_H	Setup time for SCTRL_A after DCLK_A	LVDS	0.35			ns
t_H	Setup time for SCTRL_B after DCLK_B	LVDS	0.35			ns
t_SKEW	Channel B relative to Channel A⁽²⁾⁽³⁾	LVDS	–1.51		1.51	ns

(1) See Figure 6-6 for timing requirements for LVDS.

(2) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and D_AP(15:0).

(3) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and D_BP(15:0).

Figure 6-2 SCP Timing Requirements

See Section 6.4 for f_SCPCLK, t_{SCP_DS}, t_{SCP_DH}, and t_{SCP_PD} specifications.

See Section 6.4 for t_r and t_f specifications and conditions.

Not to scale.

Refer to the Section 6.8.

Refer to Section 5 for list of LVDS pins and SCP pins.

Figure 6-3 Rise Time and Fall Time

Figure 6-4 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. See Figure 6-4.

Figure 6-5 LVDS Waveform Requirements

See Section 6.4 for V_CM, V_ID, and V_LVDS specifications and conditions.

Figure 6-6 Timing Requirements

See Section 6.8 for timing requirements and LVDS pairs per channel (bus) defining D_P(0:x) and D_N(0:x).