ZHCSJ27 November 2018 DLP650LNIR
PRODUCTION DATA.
Table 4 describes the inputs and outputs of the DLPC410 related to the control of the DLP650LNIR DMD. For more details on these signals, see the DLPC410 data sheet (DLPS024).
| PIN NAME | DESCRIPTION | I/O |
|---|---|---|
| ARST | Asynchronous active low reset | I |
| CLKIN_R | Reference clock, 50 MHz | I |
| DIN_[A,B,C,D](15:0) | LVDS DDR input for data bus A,B,C,D (15:0) | I |
| DCLKIN[A,B,C,D] | LVDS inputs for data clock (400 MHz) on bus A, B, C, and D | I |
| DVALID[A,B,C,D] | LVDS input signals used to start write sequence for bus A, B, C, and D | I |
| ROWMD(1:0) | DMD row address and row counter control | I |
| ROWAD(10:0) | DMD row address pointer | I |
| BLK_AD(3:0) | DMD mirror block address pointer | I |
| BLK_MD(1:0) | DMD mirror block reset and clear command modes | I |
| PWR_FLOAT | Used to float DMD mirrors before complete loss of power | I |
| LOAD4 | Load4 mode enable [uses DLPC410 SPARE_0 input pin (AB21)] | I |
| DMD_TYPE(3:0) | DMD type in use | O |
| RST_ACTIVE | Indicates DMD mirror reset in progress | O |
| INIT_ACTIVE | Initialization in progress. | O |
| VLED0 | System “heartbeat” signal | O |
| VLED1 | Denotes initialization complete | O |