10.1.4 DMD Interface

The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz. Data is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz. Make sure the LVDS signals have 100 Ω differential impedance. Make sure the differential signals are length-matched and are as short as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination is not necessary.