米6体育平台手机版

ZHCSRS7A August 2017 – February 2023 DLP650NE

PRODUCTION DATA

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请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

FYE|350

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).

PARAMETER		TEST CONDITIONS⁽¹⁾	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	VCC = 3.3 V, I_OH = –20 mA	2.4			V
V_OL	Low -level output voltage	VCC = 3.45 V, I_OL = 15 mA			0.4	V
I_IH	High-level input current⁽²⁾⁽³⁾	VCC = 3.45 V, V_I = VCC			250	µA
I_lL	Low-level input current	VCC = 3.45 V, V_I = 0	–250			µA
I_OZ	High–impedance output current	VCC = 3.45 V			10	µA
I_CC	Supply current⁽⁴⁾	VCC = 3.45 V			1100	mA
I_CCI	Supply current⁽⁴⁾	VCCI = 3.45 V			500	mA
I_OFFSET	Supply current⁽⁵⁾	VOFFSET = 8.75 V		10	25	mA
I_BIAS	Supply current⁽⁵⁾	VBIAS = 16.5 V		10	14	mA
I_RESET	Supply current	VRESET = –10.5 V		10	11	mA
I_TOTAL	Supply current	Total Sum			1650	mA
C_I	Input capacitance	ƒ = 1 MHz			10	pF
C_O	Output capacitance	ƒ = 1 MHz			10	pF
C_M	Reset group capacitance MBRST(14:0)	ƒ = 1 MHz all inputs interconnected, (1920 x 1080) array	330		390	pF

(1) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(2) Applies to LVCMOS input pins only; excludes the LVDS pins and MBRST pins

(3) LVCMOS input pins utilize an internal 18000-Ω passive resistor for pullup and pulldown configurations. Refer to Section 5 to determine the pullup or pulldown configuration used.

(4) To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.

(5) To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit.