During power-up, VDD must always start
and settle before VOFFSET plus tDELAY1 specified in Section 9.1, VBIAS, and VRESET voltages are applied to the
DMD.
During power-up, it is a strict requirement that
the voltage difference between VBIAS
and VOFFSET must be within the
specified limit shown in Section 6.4.
During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS.
Power supply slew rates during power-up are
flexible, provided that the transient voltage
levels follow the requirements specified in Section 6.1, in Section 6.4, and in Figure 9-1.
During power-up, LVCMOS input pins must not be
driven high until after VDD has settled
at operating voltage listed in Section 6.4.