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ZHCSN28A March 2021 – May 2022 DLP651NE

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FYP|149
- MCLG039

散热焊盘机械数据 (封装 | 引脚)

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6.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device reliability.

Parameter Name	Description	MIN	MAX	UNIT
Supply Voltage
V_DD	Supply voltage for LVCMOS core logic and LVCMOS low speed interface (LSIF) ⁽¹⁾	–0.5	2.3	V
V_DDA	Supply voltage for high speed serial interface (HSSI) receivers ⁽¹⁾	–0.3	2.2	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode ⁽¹⁾⁽²⁾	–0.5	11	V
V_BIAS	Supply voltage for micromirror electrode ⁽¹⁾	–0.5	17	V
V_RESET	Supply voltage for micromirror electrode ⁽¹⁾	–13	0.5	V
\| V_DDA – V_DD \|	Supply voltage delta (absolute value) ⁽³⁾		0.3	V
\| V_BIAS – V_OFFSET \|	Supply voltage delta (absolute value) ⁽⁴⁾		11	V
\| V_BIAS – V_RESET \|	Supply voltage delta (absolute value) ⁽⁵⁾		30	V
Input Voltage
	Input voltage for other inputs – LSIF and LVCMOS ⁽¹⁾	–0.5	2.45	V
	Input voltage for other inputs – HSSI ⁽¹⁾⁽⁶⁾	–0.2	V_DDA	V
Low speed interface (LSIF)
f_CLOCK	LSIF clock frequency (LS_CLK)		130	MHz
\| V_ID \|	LSIF differential input voltage magnitude ⁽⁶⁾		810	mV
I_ID	LSIF differential input current⁽⁷⁾		10	mA
High speed serial interface (HSSI)
f_CLOCK	HSSI clock frequency (DCLK)		1.65	GHz
\| V_ID \|	HSSI differential input voltage magnitude Data Lane ⁽⁶⁾		700	mV
\| V_ID \|	HSSI differential input voltage magnitude Clock Lane ⁽⁶⁾		700	mV
Environmental
T_ARRAY	Temperature, operating⁽⁸⁾	0	90	°C
T_ARRAY	Temperature, non-operating⁽⁸⁾	–40	90	°C
T_DP	Dew point temperature, operating and non-operating (non-condensing)		81	ºC

(1) All voltage values are with respect to the ground terminals (V_SS). The following required power supplies must be connected for proper DMD operation: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are also required.

(2) V_OFFSET supply transients must fall within specified voltages.

(3) Exceeding the recommended allowable absolute voltage difference between V_DDA and V_DD may result in excessive current draw.

(4) Exceeding the recommended allowable absolute voltage difference between V_BIAS and V_OFFSET may result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between V_BIAS and V_RESET may result in excessive current draw.

(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS and HSSI differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(7) Differential inputs must not exceed the specified limit or damage may result to the internal termination resistors. Specification applies to both the High speed serial interface (HSSI) and the low speed interface (LSI).

(8) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) shown in Figure 7-1 and the package thermal resistances using the Micromirror Array Temperature Calculation.