The DLP660TE DMD is part of a chipset that is controlled by the DLPC4420 display controller in conjunction with the DLPA100 power and motor driver. These guidelines help to design a PCB board with the DLP660TE DMD. The DLP660TE DMD board is a high-speed multilayer PCB, with primarily high-speed digital logic using dual-edge clock rates up to 400 MHz for DMD LVDS signals. The remaining traces are comprised of low speed digital LVTTL signals. TI recommends that mini power planes are used for VOFFSET, VRESET, and VBIAS. Solid planes are required for DMD_P3P3V(3.3 V), DMD_P1P8V, and Ground. The target impedance for the PCB is 50 Ω ±10% with the LVDS traces being 100-Ω ±10% differential. TI recommends using an 8-layer stack-up as described in Table 9-1.