ZHCSKV8A November 2020 – June 2022 DLP670S
PRODUCTION DATA
The DLP670S DMD is one device in a chipset controlled by the DLPC900 controller. The following guidelines are targeted at designing a functioning PCB using this DLP670S DMD chipset. The DLP670S DMD board must be a high-speed multilayer PCB containing high-speed digital logic utilizing dual edge (DDR) LVDS signals at 400-MHz clock rates. Figure 10-1 shows the DLP670S signals and the recommendations needed from and to the DLPC900 controller devices. The DLPC900 device provides the data and control to the DMD. The TPS65145, LP38513 or equivalent devices supply power to the DMD.
| Note | Signal Type | Guideline |
|---|---|---|
| A | Differential | Prevent signal noise |
| Route 100 ±10-Ω resistor | ||
| Intra-pair (P-to-N) length tolerance is ±12-mils. | ||
| DD and SCTRL must be matched to the DCLK within ±150-mils. | ||
| DCLK_C must be matched to DCLK_D within ±1.25-ns. | ||
| DCLK_A must be matched to DCLK_B within ±1.25-ns. | ||
| Do not switch routing layers except at the beginning and end of trace. | ||
| Signal routing length must not exceed 375-mm. | ||
| B | Single-ended | Prevent signal noise |
| Route single-ended signals 50 ±5-Ω | ||
| No length match requirement | ||
| C | Power | VRESET, VOFFSET, VBIAS, and VCC at the DMD must be kept within the operating limits specified in the data sheet. |
| Provide proper amount of decoupling capacitance for each voltage at the DMD |