A. See Pin Configuration and Functions for pin functions.

B. VDD must be up and stable prior to VCC2 powering up.

C. PWRDNZ has two turn on options. Option 1: PWRDNZ does not go high until VDD and VCC2 are up and stable, or Option 2: PWRDNZ must be pulsed low for a minimum of T_PWRDNZ, or 10ns after VDD and VCC2 are up and stable.

D. There is a minimum of T_{LVDS_ARSTZ}, or 2μs, wait time from PWRDNZ going high for the LVDS receiver to recover.

E. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates the PWRDNZ and disables VCC2.

F. Under power-loss conditions, where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware, PWRDNZ goes low.

G. VDD must remain high until after VCC2 goes low.

H. To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit in Section 5.4.