The DLP781TE DMD is part of a chipset that is controlled by the 两个 DLPC4420 显示控制器 in conjunction with the DLP300 micromirror driver and the DLPA100 power and motor driver. These guidelines are targeted at designing a PCB board with the DLP781TE DMD. The DLP781TE DMD board is a high-speed multi-layer PCB, with primarily high-speed digital logic utilizing dual edge clock rates up to 400MHz for DMD LVDS signals. The remaining traces are comprised of low speed digital LVTTL signals. Solid planes are required for DMD_P1P8V and Ground. The target impedance for the PCB is 50Ω ±10% with the LVDS traces being 100Ω ±10% differential. TI recommends using an 8-layer stack-up as described in Table 7-1.