米6体育平台手机版

ZHCSR38A November 2022 – September 2023 DLP801RE

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

FYV|350
- MCCC010

散热焊盘机械数据 (封装 | 引脚)

9.3 DMD Power Supply Power-Down Procedure

During power-down, VDD and VDDI must be supplied until after VCC2 is discharged to within the specified limit of ground. Refer to Section 6.4.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed in Section 6.1 and in Section 6.4.
During power-down, LVCMOS input pins must be less than specified in Section 6.4.

Figure 9-1 DMD Power Supply Sequencing Requirements

A. See Pin Configuration and Functions for pin functions.

B. VDD must be up and stable prior to VCC2 powering up.

C. PWRDNZ has two turn on options. Option 1: PWRDNZ does not go high until VDD and VCC2 are up and stable, or Option 2: PWRDNZ must be pulsed low for a minimum of T_PWRDNZ, or 10 ns after VDD and VCC2 are up and stable.

D. There is a minimum of T_{LVDS_ARSTZ}, or 2 μs, wait time from PWRDNZ going high for the LVDS receiver to recover.

E. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates the PWRDNZ and disables VCC2.

F. Under power-loss conditions, where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware, PWRDNZ goes low.

G. VDD must remain high until after VCC2 goes low.

H. To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit in Section 6.4.