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ZHCSR39B October 2022 – September 2023 DLP801XE

PRODUCTION DATA

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机械数据 (封装 | 引脚)

FYV|350
- MCCC010

散热焊盘机械数据 (封装 | 引脚)

6.1 Absolute Maximum Ratings

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

		MIN	MAX	UNIT
SUPPLY VOLTAGES
V_DD	Supply voltage for LVCMOS core logic⁽¹⁾	–0.5	2.3	V
V_DDI	Supply voltage for LVDS Interface⁽¹⁾	–0.5	2.3	V
V_CC2	Micromirror Electrode and HVCMOS voltage⁽¹⁾⁽²⁾	–0.5	11	V
V_MBRST	Input voltage for MBRST pins⁽¹⁾	–17.5	22.5	V
\|V_DDI– V_DD\|	Supply voltage delta (absolute value)⁽³⁾		0.3	V
INPUT VOLTAGES
\|V_ID\|	Input differential voltage for LVDS pins (absolute value)		500	mV
V_LVCMOS	Input voltage for all other input pins⁽¹⁾	–0.3	V_DDI+ 0.3	V
ENVIRONMENTAL
T_ARRAY	Temperature, operating⁽⁴⁾	0	90	°C
T_ARRAY	Temperature, non–operating⁽⁴⁾	–40	90	°C
T_DP	Dew point temperature, operating and non–operating (noncondensing)		81	°C

(1) All voltages are referenced to common ground V_SS. V_DD, V_DDI, and V_CC2 power supplies are all required for all DMD operating modes.

(2) V_CC2 supply transients must fall within specified voltages.

(3) Exceeding the recommended allowable voltage difference between V_DD and V_DDI may result in excessive current draw.

(4)
The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1), shown in Figure 7-1 using the Section 7.6.