ZHCSOK9A october 2021 – june 2023 DLPA300
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics Control Logic
- 6.6 5-V Linear Regulator
- 6.7 Bias Voltage Boost Converter
- 6.8 Reset Voltage Buck-Boost Converter
- 6.9 VOFFSET Regulator
- 6.10 Switching Characteristics
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.3.4 VOFFSET Regulator
The VOFFSET regulator supplies the internal VOFFSET voltage for the high voltage FET switches. The VOFFSET voltage level for the 9-μm pixel family of DMDs is 10-V during normal operation and 4.5-V during power down. The VOFFSET voltage level is configured by the DLP controller chip over the serial communication port. Four control bits select the voltage level while a fifth bit is the on/off control. The module provides two status bits to indicate latched and unlatched status bits for undervoltage (VUV) and current-limit (CL) conditions.
Figure 7-3 shows the block diagram of this module. The input decoupling capacitors are shared with other DLPA300 modules. See Section 8.2.2.1 for recommended component values.
Figure 7-3 Offset Voltage Boost Convertor
Block Diagram