ZHCSOK9A october 2021 – june 2023 DLPA300
PRODUCTION DATA
The SCP is a full duplex, synchronous, character-oriented (byte) port that allows exchange of data between the DLPC4430 or DLPC4420 display controller, and the DLPA300 micromirror driver (and other DLP devices). The display controller is the primary on the SCP bus. The DLPA300 micromirror driver is the secondary on the SCP bus.
| SIGNAL | I/O | FROM/TO | TYPE | DESCRIPTION |
|---|---|---|---|---|
| SCPCK | I | SCP bus primary to secondary | LVTTL compatible | SCP bus serial transfer clock. The host processor (primary) generates this clock. |
| SCPEN | I | SCP bus primary to secondary | LVTTL compatible | SCP bus access enable (low true). When high, secondary resets to the idle state, and SCPDO output is tristated. Pulling SCPEN low initiates a read or write access. SCPEN must remain low for an entire read/write access, and must be pulled high after the last data cycle. To abort a read or write cycle, pull SCPEN high at any point. |
| SCPDI | I | SCP bus primary to secondary | LVTTL compatible | SCP bus serial data input. Data bits are valid and must be clocked in on the falling edge of SCPCK. |
| SCPDO | O | SCP bus secondary to primary | LVTTL, open drain w/tristate | SCP bus serial data output. Data bits must clocked out on the rising edge of SCPCK. A 1-kΩ pullup resistor to the 3.3-V display controller supply is required. |
| IRQ | O | SCP bus secondary to primary | LVTTL, open drain | Not part of the SCP bus definition. Asynchronous interrupt signal from secondary to request service from the primary. A 1-kΩ pullup resistor to the 3.3-V display controller supply is required. |