The power-up and power-down sequence is important to ensure a correct operation of the DLPA3000 and to prevent damage to the DMD. The DLPA3000 controls the correct sequencing of the DMD_VRESET, DMD_VBIAS and DMD_VOFFSET to ensure a reliable operation of the DMD.

The general startup sequence of the supplies was described previously in Supply and Monitoring. The power-up sequence of the high-voltage DMD lines is especially important to prevent damaging the DMD. Damage could include, for example, that DMD mirrors get stuck or collide. A too-large delta voltage between DMD_VBIAS and DMD_VOFFSET could cause the damage and should therefore be prevented.

After PROJ_ON is pulled high, the DMD buck converters and LDOs are powered (PWR1-4) the DMD high voltage lines (HV) are sequentially enabled. First, DMD_VOFFSET is enabled. After a delay, DMD_VBIAS is enabled. Finally, after another delay, DMD_VRESET is enabled. The DLPA3000 is now fully powered and ready for starting projection.

For power down, there are two sequences: normal power down (Figure 8-17) and a fault fast power-down used in case a fault occurs (Figure 8-18).

In normal power-down mode, the power down is initiated after pulling PROJ_ON pin low. 25 ms after PROJ_ON is pulled low, DMD_VBIAS and DMD_VRESET will stop regulating. 10 ms later, DMD_VOFFSET will stop regulating. When DMD_VOFFSET stops regulating, RESET_Z is pulled low. 1 ms after the DMD_VOFFSET stops regulating, all other supplies are turned off. INT_Z remains high during the power-down sequence since no fault occurred. During power down, it is guaranteed that the HV levels do not violate the DMD specifications on these three lines. For this, it is important to select the capacitors such that C_VOFFSET is equal to C_VRESET and C_VBIAS is ≤ C_VOFFSET, C_VRESET.

The fast power-down mode (Figure 8-18) is started in case a fault occurs (INT_Z will be pulled low), for instance due to overheating. The fast power-down mode can be enabled or disabled through register FAST_SHUTDOWN_EN (0x01, bit 7). The mode is enabled by default. After the fault occurs, regulation of DMD_VBIAS and DMD_VRESET is stopped. There is 540 µs default delay time between fault and stop of regulation. After the regulation stopped, there is 4 µs default delay time before all three DMD_VRESET, DMD_VBIAS and DMD_VOFFSET high voltages lines are discharged and RESET_Z is pulled low.

The DLPA3000 is now in a standby state. It remains in standby state until the fault resolves. In case the fault resolves, a restart is initiated. It starts then by powering up PWR_3 and follows the regular power up as depicted in Figure 8-18. For proper discharge timing and levels, the capacitors such that C_VOFFSET is equal to C_VRESET and C_VBIAS is ≤ C_VOFFSET, C_VRESET.

1. Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under SPI control.
2. SUP_5P0V and SUP_2P5V rise to a precharge level with SYSPWR, and reach the full level potential after PROJ_ON is pulled high.

Figure 8-17 Power Sequence Normal Shutdown Mode

1. Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under SPI control.
2. SUP_5P0V and SUP_2P5V rise to a precharge level with SYSPWR, and reach the full level potential after PROJ_ON is pulled high.

Figure 8-18 Power Sequence Fault Fast Shutdown Mode